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posted by martyb on Thursday March 08 2018, @02:24PM   Printer-friendly
from the it's-just-a-small-RISC dept.

Wave Computing Adopts Low Power MIPS 64-bit Multi-Threaded Core

Wave Computing [...] announced today that it has selected a 64-bit Multi-Threaded processor core from MIPS Technologies for future AI solutions. Wave will use the MIPS core in its next generation of Dataflow Processing Unit (DPU) chips that will ship in Wave's future deep learning systems to handle device control functions including management of the real-time operating system (RTOS) and system-on-chip (SoC) subsystem.

From a MIPS press release:

As design complexity and software footprints continue to increase, the 64-bit MIPS architecture is being used in an even broader set of datacenter, connected consumer devices, networking products, and emerging AI applications. In addition to Wave, companies including Mobileye, Fungible, ThinCI, and DENSO, among others, are using the MIPS 64-bit processor core as they develop ground-breaking AI applications. [...] Last August, Denso group company NSITEXE, Inc. announced that it licensed the newest MIPS CPU to drive enhanced in-vehicle electronic processing.

Related: MIPS Strikes Back: 64-bit Warrior I6400 Arrives
PEZY's Next Many-Core Chip Will Include a MIPS 64-Bit CPU
ARM Cortex-A35, Snapdragon 820, and New Imagination MIPS Processors
Linux-Based, MIPS-Powered Russian All-in-One PC Launched
Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off


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  • (Score: 3, Interesting) by Snotnose on Thursday March 08 2018, @03:39PM (9 children)

    by Snotnose (1623) on Thursday March 08 2018, @03:39PM (#649513)

    Back around the turn of the century, if a manufacturer wanted to be certified for WinCE they had to pass a Microsoft-written test suite. My job was to get various CPUs to pass this test suite. One of the tests was to ensure the entire 32 bit address space was addressable. MIPs had this hardware quirk where something like 1/4 of their address space was dedicated to I/O. Microsoft had plans in place to get waivers on certain requirements, but I'm guessing I was the first one to try and make use of them. The guy I dealt with clearly didn't want to work with me, thought he was much smarter than me, and flat out didn't want to deal with my emails. Finally got MIPs certified, but man what a pain.

    That was a fun job. I got to certify the ARM, MIPS, and SH-4 for WinCE (took 2-3 month each to get the test suite running). Then a few months later I had to actually use WinCE. What a royal pain in the ass that was. WinCE was designed for embedded systems. Embedded systems need hard limits on things like interrupt latency, stack size, etc etc etc. WinCE didn't support any of these. I was trying to play video. It would go great for a minute or so, then start stuttering for no apparent reason. The root cause was WinCE doing it's nails, or whatever. There was no way to avoid it, bigger buffers didn't help because the problem was WinCE's latency issues.

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  • (Score: 2) by RamiK on Thursday March 08 2018, @05:44PM (8 children)

    by RamiK (1813) on Thursday March 08 2018, @05:44PM (#649580)

    One of the tests was to ensure the entire 32 bit address space was addressable.

    FYI Last I checked your typical x86-64 can't address more than 48bit directly or 52bit with PAE.

    Just some pointless trivia...

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    • (Score: 0) by Anonymous Coward on Thursday March 08 2018, @07:57PM (5 children)

      by Anonymous Coward on Thursday March 08 2018, @07:57PM (#649666)

      And often underappreciated. Most operating system level code is going to have to be rewritten when that gets expanded out, and given that everything bit 52 and above is used means that there might be userspace code out there that actually DOES either poll or filter those bits, meaning old code may need some major rewrites to work with full 64 bit addressing. Honestly I dislike the fact that they call them 64 bit processors without more clearly defining if they mean 64 bit addressing, or simply 64 bit integer processing.

      • (Score: 0) by Anonymous Coward on Thursday March 08 2018, @08:02PM (2 children)

        by Anonymous Coward on Thursday March 08 2018, @08:02PM (#649671)

        Operating systems are ready for full 64-bits since the beginning of amd64 support. There is no reason to implement any type of filtering in "userspace code" since it never does see the underlying physical address (every process has its own virtual address space). I'd suggest you look into how an operating system works in terms of memory management, it might be useful...

        • (Score: 2) by TheRaven on Friday March 09 2018, @10:34AM (1 child)

          by TheRaven (270) on Friday March 09 2018, @10:34AM (#649905) Journal
          A lot of userspace code assumes a 52-bit virtual address space or smaller. This lets it implement NaN boxing (common for implementing languages like JavaScript or Lua), where pointers are stored as invalid floating point NaNs (bits 52-62 all one) and numbers are represented as either valid numbers or valid NaNs. This lets you implement a discriminated union of a pointer or a double in a single 64-bit word and you just clear the top 12 bits before using the pointer.
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          • (Score: 2) by FatPhil on Friday March 09 2018, @02:09PM

            by FatPhil (863) <pc-soylentNO@SPAMasdf.fi> on Friday March 09 2018, @02:09PM (#649953) Homepage
            Glad to see 70's tech is still alive.
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      • (Score: 2) by shortscreen on Friday March 09 2018, @06:57AM (1 child)

        by shortscreen (2252) on Friday March 09 2018, @06:57AM (#649878) Journal

        The CPU insists that those unused bits remain zero (rather than just ignoring them like a 68000), so people wouldn't be tempted to put random garbage in there that would only cause problems in the future.

        • (Score: 2) by TheRaven on Friday March 09 2018, @10:43AM

          by TheRaven (270) on Friday March 09 2018, @10:43AM (#649906) Journal
          The CPU does that (except on AArch64 if you set the top-byte-ignore flag), but that doesn't stop people from storing data in the top bits and then clearing them before using the value as a pointer.
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    • (Score: 0) by Anonymous Coward on Thursday March 08 2018, @07:59PM (1 child)

      by Anonymous Coward on Thursday March 08 2018, @07:59PM (#649668)

      Pointless and incorrect. There is no PAE for amd64. You're thinking of virtual and physical address spaces. Neither is truly 64-bit wide in any current implementation.

      • (Score: 0) by Anonymous Coward on Friday March 09 2018, @07:43PM

        by Anonymous Coward on Friday March 09 2018, @07:43PM (#650185)

        A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hierarchy of in-memory paging structures located using the contents of CR3. IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses. Although 52 bits corresponds to 4 PBytes, linear addresses are limited to 48 bits; at most 256 TBytes of linear-address space may be accessed at any given time.

        ( Intel® 64 and IA-32 Architectures Software Developer’s Manual [intel.com] Ch. 4.5 IA-32E PAGING )

        The tables and diagrams explain what "direct" means here.