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Arthur T Knackerbracket [soylentnews.org] writes:

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Arthur T Knackerbracket has processed the following story [tomshardware.com]:

TSMC Readies Lower-Cost 4nm Manufacturing Tech: Up To 8.5% Cheaper

TSMC has unveiled its new 4 nm-class production technology, N4C, a new fabrication process set to enhance the company's 5nm-class production nodes by offering significant cost reductions and optimizing design efficiency.  

"We are not done with our 5nm and 4nm [technologies]," said Kevin Zhang, Vice President of Business Development at TSMC, at the company's North American Technology Symposium 2024 [tsmc.com], where the new process was revealed. "From N5 to N4, we have achieved 4% density improvement optical shrink, and we continue to enhance the transistor performance. Now we bring in N4C to our 4 nm technology portfolio. N4C allows our customers to reduce their costs by remove some of the masks and to also improve on the original IP design like a standard cell and SRAM to further reduce the overall product level cost of ownership." 

The N4C process technology is a part of TSMC’s N5/N4 node family and builds on the N4P technology. By redesigning the standard cell and SRAM cell, altering some design rules, and decreasing the number of masking layers used, TSMC plans to cut costs by up to 8.5%. These changes not only simplify the manufacturing process but also reduce the size of the dies, which could potentially improve yield due to less complexity and smaller area requirements. 

This cost-effective node uses the same design infrastructure as N4P, although it is still unclear whether IP from N5, N4, and N4P can be directly transferred to N4C-based chips. This introduces some uncertainty regarding compatibility with existing designs. We don't yet know how easy it will be to port them to N4C from N5 or N4. TSMC implies that it is going to offer the best balance between cost-benefit and design effort, with a view to encouraging the adoption of its N4C process, but the details remain to be seen. 

The introduction of N4C is strategically important for TSMC as it provides a way for customers to significantly lower their production costs for a 4nm-class node, which may drive the adoption of this process technology among customers looking for relatively low costs. The new node promises a well-adjusted combination of power, performance, and area (PPA), making it an attractive option for many of TSMC's clients. 

Given the high costs associated with 3nm-class technologies and their relatively limited advantages over nodes like N4P in terms of performance and transistor density, N4C is positioned to be a popular choice.  

TSMC expects to start producing chips using the N4C technology in 2025. With six years of experience in 5 nm-class fabrication processes by then, the company anticipates that N4C will achieve good yields and maintain lower costs, reinforcing its appeal as a cost-effective manufacturing solution in the semiconductor industry. In fact, by 2025, many of the fab tools at 5nm-capable fabs will be depreciated, so N4C and similar nodes may actually be cost-effective.

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Arthur T Knackerbracket has processed the following story [anandtech.com]:

TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its current-generation 5nm-class offerings. To that end, at its North American Technology Symposium 2024, the company introduced a new, optimized 5nm-class node: N4C.

TSMC's N4C process belongs to the company's 5nm-class family of fab nodes and is a superset of N4P, the most advanced technology in that family. In a bid to further bring down 5nm manufacturing costs, for TSMC is implementing several changes for N4C, including rearchitecting their standard cell and SRAM cell, changing some design rules, and reducing the number of masking layers. As a result of these improvements, the company expects N4C to achieve both smaller die sizes as well as a reduction in production complexity, which in turn will bring die costs down by up to 8.5%. Furthermore, with the same wafer-level defect density rate as N4P, N4C stands to offer even higher functional yields thanks to its die area reduction.

"So, we are not done with our 5nm and 4nm [technologies]," said Kevin Zhang, Vice President of Business Development at TSMC. "From N5 to N4, we have achieved 4% density improvement optical shrink, and we continue to enhance the transistor performance. Now we bring in N4C to our 4 nm technology portfolio. N4C allows our customers to reduce their costs by remove some of the masks and to also improve on the original IP design like a standard cell and SRAM to further reduce the overall product level cost of ownership."

TSMC says that N4C can use the same design infrastructure as N4P, though it is unclear whether N5 and N4P IP can be re-used for N4C-based chips. Meanwhile, TSMC indicates that it offers various options for chipmakers to find the right balance between cost benefits and design effort, so companies interested in adopting a 4nm-class process technologies could well adopt N4C.

The development of N4C comes as many of TSMC's chip design customers are preparing to launch chips based on the company's final generation of FinFET process technology, the 3nm N3 series. While N3 is expected to be a successful family, the high costs of N3B have been an issue, and the generation is marked by diminishing performance and transistor density returns altogether. Consequently, N4C could well become a major, long-lived node at TSMC, serving as a good fit for customers who want to stick to a more cost-effective FinFET node.

"This is a very significant enhancement, we are working with our customer, basically to extract more value from their 4 nm investment," Zhang said.

TSMC expects to start volume production of N4C chips some time next year. And with TSMC having produced 5nm-class for nearly half a decade at that point, N4C should be able to hit the ground running in terms of volume and yields.

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