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takyon writes:

Marvell at FMS 2019: NVMe Over Fabrics Controllers, AI On SSD

Taking things to the logical next step, Marvell also announced a native Ethernet/NVMeoF SSD controller. The 88SS5000 is effectively their 88SS1098 NVMe controller with the PCIe interface replaced by the dual 25GbE interface used by the NVMe to Ethernet converter. This new single-chip solution for Ethernet-attached SSDs helps cut costs and power consumption, making the whole idea more palatable to datacenter customers. Marvell showed samples of this controller paired with 8TB of Toshiba 96L 3D TLC NAND and 12GB of DDR4 DRAM.

Looking further into the future, Marvell shared their take on the idea of Computational Storage—SSDs that do more than just store data. Marvell is working to integrate a Machine Learning engine into future SSD controllers, allowing inferencing tasks to be offloaded from CPUs or GPUs onto the SSDs that already store the data being processed. The hardware setup is basically the same mess of cables connecting FPGAs to Flash that Marvell has shown in previous years, but on the software side their demo has matured greatly.

In addition to demonstrating realtime object recognition using a pre-trained model, Marvell now has a system to perform offline recognition on videos stored on the SSD. Their demo presented the results of this recognition as a graph showing which objects were recognized over the duration of a video. There was also a content-aware search engine that would return the segments of stored videos that depict the requested objects. For the demo, this functionality was exposed through a simple web interface. In production, the envisioned use case is to have an application server aggregating results from an array of content-aware SSDs that each perform some kind of analytics on their share of the overall dataset.

Original Submission

takyon writes:

Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor

The Arm server ecosystem is well alive and thriving, finally getting into serious motion after several years of false-start attempts. Among the original pioneers in this space was Cavium, which went on to be acquired by Marvell in 2018. Among the company's server CPU products is the ThunderX line; while the first generation ThunderX left quite a lot to be desired, the ThunderX2 was the first Arm server silicon that we deemed viable and competitive against Intel and AMD products. Since then, the ecosystem has accelerated quite a lot, and only last week we saw how impressive the new Amazon Graviton2 with the N1 chips ended up. Marvell didn't stop at the ThunderX2, and had big ambitions for its newly acquired CPU division, and today is announcing the new ThunderX3.

The ThunderX3 is a continuation and successor to then-Cavium's custom microarchitecture found in the TX2, adopting a lot of the key characteristics, most notably the capability of 4-way SMT. Adopting a new microarchitecture with higher IPC capabilities, the new TX3 also ups the clock frequencies, and now hosts up to a whopping 96 CPU cores, allowing the chip to scale up to 384 threads in a single socket.

Related: Marvell Technology to Buy Cavium for $6 Billion
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80-Core Arm CPU To Bring Lower Power, Higher Density To A Rack Near You

Original Submission

takyon writes:

Hot Chips 2020: Marvell Details ThunderX3 CPUs - Up to 60 Cores Per Die, 96 Dual-Die in 2021

Today as part of HotChips 2020 we saw Marvell finally reveal some details on the microarchitecture of their new ThunderX3 server CPUs and core microarchitectures. The company had announced the existence of the new server and infrastructure processor back in March, and is now able to share more concrete specifications about how the in-house CPU design team promises to distinguish itself from the quickly growing competition that is the Arm server market.

[...] Marvell started off the HotChips presentation with a roadmap of its products, detailing that the ThunderX3 generation isn't merely just a single design, but actually represents a flexible approach using multiple dies, with the first generation 60-core CN110xx SKUs using a single die as a monolithic design in 2020, and next year seeing the release of a 96-core dual-die variant aiming for higher performance.

The use of a dual-die approach like this is very interesting as it represents a mid-point between a completely monolithic design, and a chiplet approach from vendors such as AMD. Each die here is identical in the sense that it can be used independently as standalone products.

Some details about the CPUs and the 4-way SMT were given in the presentation. TDPs will range from 100 Watts to 240 Watts.

Previously: Marvell Announces ThunderX3, an ARM Server CPU With 96 Cores, 384 Threads

Original Submission

takyon writes:

Silicon Motion Launches PCIe 4.0 NVMe SSD Controllers

Silicon Motion has announced the official launch of their first generation of PCIe 4.0-capable NVMe SSD controllers. These controllers have been on the roadmap for quite a while and have been previewed at trade shows, but the first models are now shipping. The high-end SM2264 and mainstream SM2267/SM2267XT controllers will enable consumer SSDs that move beyond the performance limits of the PCIe 3.0 x4 interface that has been the standard for almost all previous consumer NVMe SSDs.

The high-end SM2264 controller is the successor to Silicon Motion's SM2262(EN) controllers, and the SM2264 brings the most significant changes that add up to a doubling of performance. The SM2264 still uses 8 NAND channels, but now supporting double the speed: up to 1600MT/s. The controller includes four ARM Cortex R8 cores, compared to two cores on SMI's previous client/consumer NVMe controllers. As with most SSD controllers aiming for the high end PCIe 4.0 product segment, the SM2264 is fabbed on a smaller node: TSMC's 12nm FinFET process, which allows for substantially better power efficiency than the 28nm planar process used by the preceding generation of SSD controllers. The SM2264 also includes support for some enterprise-oriented features like SR-IOV virtualization, though we probably won't see that enabled on consumer SSD products. The SM2264 also includes the latest generation of Silicon Motion's NANDXtend ECC system, which switches from a 2kb to 4kB codeword size for the LDPC error correction.

Also at Guru3D.

Related: Silicon Motion Controller to Enable High Speed, Low Cost Portable USB SSDs

Original Submission