Arthur T Knackerbracket has found the following story:
Scientists at the Tokyo Institute of Technology (Tokyo Tech) and the University of Tokyo (UTokyo) have developed a new three-valued memory device inspired by solid lithium-ion batteries. The proposed device, which has an extremely low energy consumption, may be key for the development of more energy-efficient and faster random-access memory (RAM) components, which are ubiquitous in modern computers.
[...] A research team from Tokyo Tech led by Prof. Taro Hitosugi and student Yuki Watanabe recently reached a new milestone in this area. These researchers had previously developed a novel memory device inspired by the design of solid lithium-ion batteries. It consisted of a stack of three solid layers made of lithium, lithium phosphate and gold. This stack is essentially a miniature low-capacity battery that functions as a memory cell; it can be quickly switched between charged and discharged states that represent the two possible values of a bit. However, gold combines with lithium to form a thick alloy layer, which increases the amount of energy required to switch from one state to the other.
In their latest study, the researchers created a similar three-layer memory cell using nickel instead of gold. They expected better results using nickel because it does not easily form alloys with lithium, which would lead to lower energy consumption when switching. The memory device they produced was much better than the previous one; it could actually hold three voltage states instead of two, meaning that it is a three-valued memory device. "This system can be viewed as an extremely low-capacity thin-film lithium battery with three charged states," explains Prof. Hitosugi. This is a very interesting feature with potential advantages for three-valued memory implementations, which may be more area efficient.
More information: Yuki Watanabe et al, Low-Energy-Consumption Three-Valued Memory Device Inspired by Solid-State Batteries, ACS Applied Materials & Interfaces (2019). DOI: 10.1021/acsami.9b15366
(Score: 0) by Anonymous Coward on Friday November 29 2019, @04:20AM (3 children)
"... developed ... proposed ..."
So did they actually build a prototype, or is it merely "proposed"?
(Score: 2) by takyon on Friday November 29 2019, @05:06AM (2 children)
https://pubs.acs.org/doi/10.1021/acsami.9b15366 [acs.org]
It seems that they did make it. There is a single photo in the paper.
Looks like this would be non-volatile, if nothing else.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by c0lo on Friday November 29 2019, @05:56AM (1 child)
Confirmed, the photo is non-volatile.
I mean, I looked at the photo for about 10 mins at Australian-summer room temperatures and it didn't evaporate. (grin)
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Otherwise, the memory is volatile for some time/temperature values
https://www.youtube.com/@ProfSteveKeen https://soylentnews.org/~MichaelDavidCrawford
(Score: 3, Funny) by takyon on Friday November 29 2019, @06:31AM
When you cross battery vaporware with emerging memory technologies, you get the vaporwave charge dissipation volatilish memory.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by c0lo on Friday November 29 2019, @05:04AM (1 child)
Switch time is not yet measured, but TFA estimates it in the (lousy) 5Mhz range.
For comparison, SDRAM has read access in the 5ns range [electronics-notes.com] with memory clock freq in the 133-200MHz range [electronics-notes.com]
https://www.youtube.com/@ProfSteveKeen https://soylentnews.org/~MichaelDavidCrawford
(Score: 2) by shortscreen on Friday November 29 2019, @02:00PM
5ns would be the minimum time for bus transfers (ie. 200MHz) from an on-chip buffer, not the random access time which is more like 30ns.