Chip world veterans gather to design customizable, chiplet-based RISC-V server chips
A Silicon Valley startup is stepping out of stealth mode today, publicly vowing to supply high-performance data-center-class RISC-V processors.
Ventana Micro Systems said since its founding in 2018 it has secured $53m in funding in series A and B rounds, the latter of which totaled $38m and was led by Marvell founders Sehat Sutardja and Weili Dai.
It is hoped the first samples of its 64-bit RISC-V processors will be shared with customers in the second half of next year, and ship in volume in the first half of 2023. It's worth remembering that big biz rarely significantly commits to using someone's silicon until it reaches second generation; the first generation is mostly for evaluation of the platform, which is where Ventana is at right now.
The processors, CEO and cofounder Balaji Baktha explained to us, will use a chiplet approach, as seen with AMD and lately Intel. That is to say, each chip will contain a number of discrete dies – some with CPU cores, some with custom acceleration, and others with IO and memory interfaces – interconnected within a single package.
[...] Ventana's compute dies each feature 16 RISC-V cores. Baktha said these out-of-order, four-wide superscalar cores should outperform RV64 rivals and at least match Arm's Neoverse data-center-class CPUs.
(Score: 1) by AlienInterview on Friday September 03 2021, @03:39PM (4 children)
I'd love to see the competition show up. I've also seen what seems like every single open-source hardware project fail with the notable exception of the Raspberry Pi.
I wonder how they expect to survive competition from other CPU vendors.
(Score: 2) by Dr Spin on Friday September 03 2021, @05:37PM
I hope they go for computation-per-watt like Oracle (but without Larry Ellison).
Preferably with a low end entry level offering - In 2U rack units that idle at sub 50Watts, but can spin up to
(maybe) over 500W with lots of relatively simple cores, rather than insanely complex un-debuggable stuff.
Some people will need test beds if they are going to deploy at scale. Others won't want the whole rack
to draw power when only some units are working flat out. Don't just save the planet -save my electric bill too!
Of course, mega-power installations are needed, but don't forget that tall trees from little acorns grow!
Warning: Opening your mouth may invalidate your brain!
(Score: 4, Informative) by maxwell demon on Friday September 03 2021, @07:13PM
Note that RISC-V is not an open hardware (though you certainly can make RISC-V open hardware). What's open is the ISA; the actual implementation may be completely proprietary.
An analogy in software would be e.g. the HTTP protocol: The protocol itself is free to use, but the web server that interprets the requests may still be proprietary.
The Tao of math: The numbers you can count are not the real numbers.
(Score: 0) by Anonymous Coward on Saturday September 04 2021, @04:51PM (1 child)
Check out Crowd Supply. All hardware sold via Crowd Supply is open.
And, Raspberry Pie was rejected by most folks who were proponents of open hardware / software because it used a Broadcom SoCs that require binary blobs even to boot, and the SoC docs are hidden behind NDAs.
Tons of freer alternatives to the Raspberry Pie, like Pine64 and Beaglebone.
(Score: 0) by Anonymous Coward on Wednesday September 08 2021, @03:31PM
And the Pine series stuff is split between Allwinner and Rockchip cores, neither of which have been exceptionally well documented or open source friendly, although perhaps still better than Broadcom.
There hasn't really been an 'open architecture' since the PC clone era of the 1990s. I would love to see a replacement, but so far we haven't had it.