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Intel's 5-Core Lakefield Chip Appears in Database

posted by martyb on Wednesday September 04 2019, @08:34PM   Printer-friendly
from the and-the-little-core-could-outcompute-a-90s-mainframe dept.

takyon writes:

This Bizarre 5-Core Chip Could Be Intel's New Lakefield 3D Foveros CPU

Intel's upcoming 3D-stacked processor, codename Lakefield, has recently popped up in the 3DMark database. Chip detective TUM_APISAK managed to take a screenshot of the 3DMark entry.

Intel Lakefield will be the first processors to feature the chipmaker's 3D Foveros packaging. Foveros is a technology that essentially allows Intel to stack chips one on top of the other, equivalent to what storage manufacturers are doing with some new types of 3D NAND (string stacking).

According to 3DMark's report, the unidentified processor is equipped with five cores, which concurs with the core configuration for Intel's Lakefield chips. As you recall, Lakefield utilizes a design that's similar to ARM's big.LITTLE architecture. Intel complements the powerful core with other slower and more energy-efficient cores.

In Lakefield's case, Intel plans to endow the processor with one Sunny Cove core and four accompanying Atom Tremont cores. The chipmaker will cook up Lakefield chips with a combination of manufacturing process. Intel uses the 10nm node for the compute die and the 22nm node for the base die.

I'd like to see configurations with 1 small core for every 4 big cores, with the small cores handling low-level and background tasks.

Previously: Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration
AMD Plans to Stack DRAM and SRAM on Top of its Future Processors
Intel Reveals Three New Packaging Technologies for Stitching Multiple Dies Into One Processor

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  • (Score: 0) by Anonymous Coward on Wednesday September 04 2019, @08:37PM (3 children)

    by Anonymous Coward on Wednesday September 04 2019, @08:37PM (#889680)

    This seems to be news from some guy on twitter. No one knows what his job is, etc.

  • (Score: 2) by mhajicek on Wednesday September 04 2019, @08:39PM

    by mhajicek (51) on Wednesday September 04 2019, @08:39PM (#889681)

    Will it be big endian or little endian?

    I'd like to see four big cores and maybe eight little.

    --
    The spacelike surfaces of time foliations can have a cusp at the surface of discontinuity. - P. Hajicek

  • (Score: 0) by Anonymous Coward on Wednesday September 04 2019, @08:42PM (3 children)

    by Anonymous Coward on Wednesday September 04 2019, @08:42PM (#889683)

    How do they dissipate heat in stacked chips?

    • (Score: 2) by takyon on Wednesday September 04 2019, @09:33PM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday September 04 2019, @09:33PM (#889701) Journal

      Passively:

      The chips will arrive in 5W and 7W configurations.

      At those TDPs, you probably don't need a fan.

      3DSoC will supposedly target as low as sub-1W TDP by moving the memory even closer than that. Maybe that's the future: 3D chips, ultra low TDPs, but with better performance than today's 200 Watt egg fryers. As long as you can keep everything within the on-chip memory.

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    • (Score: 2) by richtopia on Thursday September 05 2019, @12:06AM

      by richtopia (3160) on Thursday September 05 2019, @12:06AM (#889749) Homepage Journal

      The comment at Hot Chips was thermals are not an issue. However, Lakefield is the first deployment of Foveros and we have yet to see real world deployment in any form factor.

      07:45PM EDT - Q: Can you scale to higher power, with like a discrete GPU on top? How does that affect die rules? A: We don't see power limits, we think it will scan the entire range of the spectrum. Or the die to die scaling. It's a question of technology and ramping, then power delivery. It's all about working out the losses. We don't see a big limit from limiting 3D stacking.

      07:46PM EDT - Q: Can you stack more dies? Thermals? A: Foveros is CoWoP with Silicon on Silicon, there should be no limit. Benefits of attaching many chiplets. Other pratical limits in architecture partitioning. Our goal is to drive it to many chiplets.

      https://www.anandtech.com/show/14773/hot-chips-31-live-blogs-intel-lakefield-and-foveros [anandtech.com]

    • (Score: 2) by mhajicek on Thursday September 05 2019, @05:36AM

      by mhajicek (51) on Thursday September 05 2019, @05:36AM (#889884)

      By melting cheese.

      --
      The spacelike surfaces of time foliations can have a cusp at the surface of discontinuity. - P. Hajicek

  • (Score: 2) by takyon on Wednesday September 04 2019, @09:44PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday September 04 2019, @09:44PM (#889708) Journal

    Intel seems to have stuffed all of its best new ideas into this chip. The x86 equivalent of ARM's big.LITTLE, DRAM on package (not sure if that's 1 GB or 4 GB total), mixing of process nodes, and their best APU graphics (until 128-256 EU Xe/Gen12 graphics next year).

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