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posted by martyb on Thursday February 20 2020, @04:11PM   Printer-friendly

Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. have designed the world's smallest all-digital phase-locked loop (PLL). PLLs are critical clocking circuits in virtually all digital applications, and reducing their size and improving their performance is a necessary step to enabling the development of next-generation technologies.

[...] The entire all-digital PLL fits in a 50 × 72 μm2 region, making it the smallest PLL to date.

A core building block of SoC devices is the phase-locked loop (PLL), a circuit that synchronizes with the frequency of a reference oscillation and outputs a signal with the same or higher frequency.

PLLs generate 'clocking signals', whose oscillations act as a metronome that provides a precise timing reference for the harmonious operation of digital devices.

[...] Manufacturers have been racing to develop increasingly smaller semiconductors. 7 nm semiconductors (a massive improvement over their 10 nm predecessor) are already in production, and methods to build 5 nm ones are now being looked at.

However, in this endeavor stands a major bottleneck. Existing PLLs require analog components, which are generally bulky and have designs that are difficult to scale down.

Scientists at Tokyo Tech and Socionext Inc., led by Prof. Kenichi Okada, have addressed this issue by implementing a 'synthesizable' fractional-N PLL, which only requires digital logic gates, and no bulky analog components, making it easy to adopt in conventional miniaturized integrated circuits.


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  • (Score: 4, Interesting) by Dr Spin on Thursday February 20 2020, @05:29PM (4 children)

    by Dr Spin (5239) on Thursday February 20 2020, @05:29PM (#960359)

    Some existing PLLs may require analog components, but the concept of a digital one is not exactly new. I used a digital PLL with no analogue components to make a data separator for ST506 using SSI TTL in about 1980, and, AFAICT, that was 40 years ago. I am not sure the concept was even new when I did it.

    I think I used a COTS phase-lock system with programmable divide by N or N+1 in a frequency agile selective calling radio design around that time too. It was able to transmit or receive any frequency in steps of 25kHz across Band II by programming the division ratio. (Miy own one could - customers had an EPROM that could only use frequencies they had the legal right to use).

    --
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  • (Score: 3, Interesting) by PartTimeZombie on Thursday February 20 2020, @09:24PM (2 children)

    by PartTimeZombie (4827) Subscriber Badge on Thursday February 20 2020, @09:24PM (#960452)

    1980 was 10 years ago.

    • (Score: 0) by Anonymous Coward on Friday February 21 2020, @01:08AM

      by Anonymous Coward on Friday February 21 2020, @01:08AM (#960533)

      Yet 1984 is still coming next year ...

    • (Score: 0) by Anonymous Coward on Friday February 21 2020, @06:04AM

      by Anonymous Coward on Friday February 21 2020, @06:04AM (#960612)

      Only in New Zealand and Queensland.

  • (Score: 0) by Anonymous Coward on Friday February 21 2020, @01:53AM

    by Anonymous Coward on Friday February 21 2020, @01:53AM (#960551)

    Some existing PLLs may require analog components, but the concept of a digital one is not exactly new.

    The fact that was integrated on the same circuit (so you don't have access to the analog part) doesn't necessary make it entirely digital.
    Those VCO-s exclusively in digital (no ADC/DAC involved) are a pain.

    Not totally related, but there you have it: just 2% helium in the environ will kill your iPhone [youtube.com] (it will recover after some days).
    Has to do with the use of microelectromechanical oscillators [wikipedia.org] (a tuning fork carved in silicon) because of a smaller footprint than a quartz oscillator. Turns out helium diffuses in silicon and strongly alters the resonance frequency.