New information has emerged about China's exascale plans, which are a part of China's 13th five-year plan for 2016-2020. Despite U.S.-imposed export restrictions on processors, two 100 petaflops systems will be launched sometime during 2016, possibly as soon as the 2016 International Supercomputing Conference in June. One of these systems will be an upgrade to Tianhe-2, and both may utilize homegrown accelerators.
At least one exascale prototype system will be built prior to a 1 exaflops system:
The exascale prototype will be about 512 nodes, offering 5-10 teraflops-per-node, 10-20 Gflops/watt, point to point bandwidth greater than 200 Gbps. MPI latency should be less than 1.5 µs, said [Beihang University Professor Depei] Qian. Development will also include system software and three typical applications that will be used to verify effectiveness. From there, work will begin on an efficient computing node and a scheme for high-performance processor/accelerator design.
"Based on those key technology developments, we will finally build the exascale system," said Qian. "Our goal is not so ambitious – it is to have exaflops in peak. We are looking for a LINPACK efficiency of greater than 60 percent. Memory is rather limited, about 10 petabytes, with exabyte levels of storage. We don't think we can reach the 20 megawatts system goal in less than five years so our goal is about 35 megawatts for the system; that means 30 Gflops/watt energy efficiency. The expected interconnect performance is greater than 500 Gbps."
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The Platform reports that CPU export restrictions to Chinese supercomputing centers may have backfired. Tianhe-2 has remained the world's top supercomputer for the last five iterations of the TOP500 list using a heterogeneous architecture that mixes Intel's Xeon and Xeon Phi chips. Tianhe-2 will likely be upgraded to Tianhe-2A within the next year (rather than by the end of 2015 as originally planned), nearly doubling its peak performance from 54.9 petaflops to around 100 petaflops, while barely raising peak power usage. However, instead of using a new Intel Xeon Phi chip, a homegrown "China Accelerator" and novel architecture will be used.
A few details about the accelerator are known:
Unlike other [digital signal processor (DSP)] efforts that were aimed at snapping into supercomputing systems, this one is not a 32-bit part, but is capable of supporting 64-bit and further, it can also support both single (as others do) and double-precision. As seen below, the performance for both single and double precision is worth remarking upon (around 2.4 single, 4.8 double teraflops for one card) in a rather tiny power envelope. It will support high bandwidth memory as well as PCIe 3.0. In other words, it gives GPUs and Xeon Phi a run for the money—but the big question has far less to do with hardware capability and more to do with how the team at NUDT will be able to build out the required software stack to support applications that can gobble millions of cores on what is already by far the most core-dense machine on the planet.
Original Submission
China may become the first country to turn on a 100 petaflops supercomputer, just one order of magnitude away from "exascale":
A little over one year ago, export blocks put in place by the US government threatened to derail China's plans to upgrade its Tianhe-2 supercomputer, the world's fastest since June 2013, to its originally planned peak capacity of 100 petaflops. At the time, many in the industry anticipated that the efforts to block China's supercomputing capability by banning access to US technology from Intel and other hardware vendors would backfire.
Indeed, China was sufficiently incentivized to redouble efforts on its homegrown supercomputing effort and it had the cash from the squashed Intel deal to do it. A couple months after news of the blacklist came out, China revealed plans to build not one, but two 100-petaflops supercomputers using a variety of native chip, accelerator and interconnect technologies. One of these systems was a fully-realized Tianhe-2, which was slated for a late-2016 launch.
VR World, the same publication who broke the blacklisting story last year, is now reporting that China is on track to announce a 100-petaflops supercomputer in June, during the 2016 International Supercomputing Conference in Frankfurt, Germany. China had originally said it would have such a system in late-2016, but this is the same country that launched its 33-petaflops (LINPACK) Tianhe-2 two years early.
The TOP500 and Green500 lists, measuring the fastest and most power efficient supercomputers respectively, are to be "merged" beginning in June 2016:
The TOP500 and Green500 lists will continue to remain separate, but all submission data will now be collected via a single online portal at http://top500.org/submit. Submission instructions are to be found on both the TOP500 and Green500 sites. The joint power submission rules are now online.
Going forward, the ISC Group will host and maintain the web presence of Green500, which is currently undergoing a re-design to reflect the integration. The new site will be officially launched at the ISC High Performance conference in Frankfurt, Germany this June. The 47th TOP500 list, and the 19th Green500 list, will be presented in a historical ceremony during this year's conference opening session.
While the TOP500 list has included estimated supercomputer power consumption for years, allowing you to perform a FLOPS/Watt calculation, the Green500 list has apparently used a different set of stricter rules. Both lists will now use the same joint power submission rules.
The integration of the two lists reflects the growing importance of power efficiency in supercomputing. The ideal target for the first 1 exaflops supercomputing systems is around 20-25 megawatts, but the first system may end up with a total power consumption of around 35 megawatts.
Here's our November 2015 TOP500 and Green500 reporting.
(Score: 3, Informative) by Gravis on Friday May 06 2016, @01:59AM
of course it will, have you seen the Top500 stats?! [wikimedia.org]
(Score: 1, Interesting) by Anonymous Coward on Friday May 06 2016, @02:02AM
The second 100 petaflops system (Sunway) will use the next-generation Chinese-made ShenWei chips and will be implemented together with a general purpose cluster system of 1 petaflops performance. This configuration is designed to meet a wide variety of application requirements.
...
The professor emphasized that China’s “self-control” strategy to eliminate dependence on foreign tech doesn’t just refer to the processor and other hardware. “One of the efforts reflected in our plan is to develop parallel algorithms and parallel libraries for the system to improve the capability of developing modern-scale systems,” he said.
I guess this is referring to foreign chips? I thought China had everyone's design plans anyway.
(Score: 2) by Scruffy Beard 2 on Friday May 06 2016, @03:51AM
They at least make a show of honouring Industrial Protectionism.
Anyway, the best chips are barred by US export restrictions. By actually doing their own research, they may be able to leap ahead of western designs.
(Score: 1, Interesting) by Anonymous Coward on Friday May 06 2016, @04:21AM
Intel's marketing/sales department has all but killed processor advancement. And AMD no longer nipping at their heels has cemented it.
The real reason for those job cuts, product line trimmings, etc is because Intel has been relying more and more on third party IP, and less on nuturing its own internal technical resources.
(Score: 2) by takyon on Friday May 06 2016, @12:21PM
AMD Zen could bring some excitement back to x86. Emphasis on "could". Multithreaded performance will increase due to the move from CMT to SMT. Will it be a 40% improvement? Perhaps in cases where Bulldozer/Excavator was extremely weak. If the core counts remain at up to 6-8 for mainstream chips, then the performance recovery along with the still high core counts could vault it over Intel's quad core chips. Unfortunately, it doesn't look like AMD will produce laptop chips with more than 4 cores.
The real excitement over at Intel seems to be in the massively parallel stuff, like Xeon Phi. Those chips see 2-3x improvements in FLOPS/W every generation. Eventually we will see some fundamental improvements over CMOS as the industry looks for low cost ways to boost performance (SiGe, nanotubes, stacked transistors, etc.)
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