SK Hynix to Manufacture 48 GiB and 96 GiB DDR5 Modules
Today SK Hynix is announcing the sampling of its next generation DDR5 memory. The headline is the commercialization of a new 24 gigabit die, offering 50% more capacity than the leading 16 gigabit dies currently used on high-capacity DDR5. Along with reportedly reducing power consumption by 25% by using SK Hynix's latest 1a nm process node and EUV technology, what fascinates me most is that we're going to get, for the first time in the PC space (to my knowledge), memory modules that are no longer powers of two.
For PC-based DDR memory, all the way back from DDR1 and prior, memory modules have been configured as a power of two in terms of storage. Whether that's 16 MiB to 256 MiB to 2 GiB to 32 GiB, I'm fairly certain that all of the memory modules that I've ever handled have been powers of two. The new announcement from SK Hynix showcases that the new 24 gigabit dies will allow the company to build DDR5 modules in capacities of 48 GiB and 96 GiB.
To be clear, the DDR5 official specification actually allows for capacities that are not direct powers of two. If we look to other types of memory, powers of two have been thrown out the window for a while, such as in smartphones. However PCs and Servers, as least the traditional ones, have followed the power of two mantra. One of the changes in memory design that is now driving regular modules to non-power of two capacities is that it is getting harder and harder to scale DRAM capacities. The time it takes to figure out the complexity of the technology to get a 2x improvement every time is too long, and memory vendors will start taking those intermediate steps to get product to market.
These are for server RDIMMs, at least for now.
Related: SK Hynix Begins Production of 18 GB LPDDR5 Memory... for Smartphones
Samsung Developing 24Gb DDR5 ICs: 768GB DDR5 Modules Possible
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SK Hynix Commences Mass Production of 18GB LPDDR5 RAM Chips for Smartphones With 6,400Mbps Speeds
Android phone makers will continue to push the limits of hardware specifications, and from the looks of it, SK Hynix will lend out more than just a helping hand. The memory manufacturer today announced that it has started mass production of 18GB LPDDR5 RAM chips for flagship smartphones, meaning that premium handsets touting more memory than notebooks will become a commonplace.
SK Hynix claims that its 18GB LPDDR5 RAM for smartphones can operate up to 6,400Mbps, making it around 20 percent faster than the previous-generation LPDDR5 RAM, which could run up to 5,500Mbps. The manufacturer also mentions that it has supplied ASUS with these DRAM chips for the upcoming ROG Phone 5 flagship. Keep in mind that during a specifications leak, the ROG Phone 5 was spotted with the aforementioned RAM count.
Why does a smartphone need 18 GB of memory instead of the previous 16 GB? From the press release:
"This product will improve the processing speed and image quality by expanding the data temporary storage space, as the capacity increases compared to the previous 16GB product," an official from the company said.
So we will see smartphones with 18 GB of RAM, or perhaps smartphones or laptops with 16/32 GB of error correction code (ECC) LPDDR5 memory.
Previously: Samsung Begins Mass Producing 12 GB DRAM Packages for Smartphones
Samsung Mass Producing LPDDR5 DRAM (12 Gb x 8 for 12 GB Packages)
Get Ready for Smartphones with 16 GB of RAM
Samsung Announces Mass Production of 16 GB LPDDR5 DRAM Packages
The new 36 Gbps GDDR7 standard offers 50% improved speeds over the current 24 Gbps GDDR6X one from Micron. Peak GDDR7 bandwidth could reach 1.7 TB/s with a 384-bit bus. Samsung also plans to release 32 Gb DDR5 chips this year, and envisions a future where 1000-layer V-NAND storage could be possible by 2030.
[...] Furthermore, the 8.5 Gbps LPDDR5X DRAM solutions for mobile phones and ultrabooks are also expected to see increased adoption throughout the coming year.
The latest graphics cards from Nvidia, AMD, and Intel use GDDR6 or GDDR6X memory.
24 Gb DDR5 chips have already been announced as a stopgap between 16 Gb and 32 Gb, enabling memory modules with unusual capacities, e.g. 48 GiB instead of 32 or 64.
The 3D NAND currently in use by the industry has around 176 to 232 layers, so reaching 1000 layers could lead to quintupled SSD capacities.
(Score: 2) by Freeman on Thursday December 16 2021, @02:42PM (1 child)
You start getting that large and Puppy Linux's, load everything into RAM starts to make a lot more sense. It's why Puppy Linux always feels snappy once it's loaded. They load the OS, etc. into RAM.
Joshua 1:9 "Be strong and of a good courage; be not afraid, neither be thou dismayed: for the Lord thy God is with thee"
(Score: 3, Interesting) by takyon on Thursday December 16 2021, @03:22PM
Ignoring the currently crazy DDR5 prices [notebookcheck.net], $/GiB has remained relatively stagnant [jcmit.net] for years. It's between about $3.12 to $3.75 per GiB, making a hypothetical single 48 GiB stick for consumers no less than $150. $300 for dual channel.
JEDEC allows up to 128 GiB consumer UDIMMs (512 GiB in 4 slots), and anticipates the development of 64 Gib dies rather than the 24 Gib used here. That might be the key to getting prices down, along with more class action lawsuits.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by Mojibake Tengu on Thursday December 16 2021, @07:00PM (1 child)
Physical address space on AMD64 architecture is currently limited to 48 bits by ISA design, so memory manufacturers still have a plenty of space for improvement.
For CPU manufacturer, just adding more channels to Infinity Fabric would be trivial update.
Rust programming language offends both my Intelligence and my Spirit.
(Score: 0) by Anonymous Coward on Wednesday December 29 2021, @11:19AM
That was the last I heard Intel/AMD were doing and I think there was another plan to expand out to 54 bit, but it's starting to get into the flag bits they'd put on the high order bits of the address pointers.
(Score: 2) by hendrikboom on Saturday December 18 2021, @02:52AM
How likely are current computers to be able to properly recognise the non-power-of-two chips and access them properly?
How do the chips tell the computer their capacity, anyway?