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posted by Fnord666 on Monday May 14 2018, @10:25PM   Printer-friendly
from the hot-tech dept.

The Taiwan Semiconductor Manufacturing Company (TSMC) has revealed a manufacturing technique (called wafer-on-wafer or WoW) that could allow CPUs and GPUs to take their first step towards vertical scaling:

Instead of one wafer per chip, future GPUs may include two or more wafers stacked vertically, which would double the performance without the need to develop new horizontal designs every 2 years. A dual wafer setup, for example, would be achieved by flipping the upper wafer over the lower one, binding both via a flip-chip package. Thus, future GPUs could include multiple wafers in one die and the operating system could detect it as a multi-processor graphics card, eliminating the need for SLI setups.

One shortcoming for this technology would be its lower manufacturing yields for sizes lower than 16 nm. If one of the stacked wafers does not pass the QA, the entire stack is discarded, leading to low yields and poor cost effectiveness. TSMC is currently working to improve this technology so that sub-12 nm processes could equally benefit from it.

Not discussed is how to deal with the heat generated in such a stack.

See also: Here's why Intel and AMD's 7nm CPU revolution is so important to the future of PCs


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  • (Score: 2) by Runaway1956 on Tuesday May 15 2018, @01:11AM (4 children)

    by Runaway1956 (2926) Subscriber Badge on Tuesday May 15 2018, @01:11AM (#679870) Homepage Journal

    one of the stacked wafers does not pass the QA, the entire stack is discarded,

    AMD has a long history of marketing chips that fail QA tests as a lower rated CPU. That is, a CPU that was intended to clock up to 3 Ghz has problems at 2.2 Ghz, is clocked down to 2 Ghz, and marketed as a 2 Ghz CPU. In such cases, AMD doesn't make the profit they would have wished, but they still recover their investment in that particular chip. Intel is less "transparent", but they market a variety of chips with various capabilities. It doesn't take any stretch of the imagination to envision their top performing chips passing every QA test, while those that don't quite make the cut are marketed as a lesser chip. The only restriction would be, architecture. You can't downgrade a chip to a class of chips with fewer pins, or entirely different voltages.

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  • (Score: 2) by requerdanos on Tuesday May 15 2018, @01:53AM

    by requerdanos (5997) Subscriber Badge on Tuesday May 15 2018, @01:53AM (#679895) Journal

    You can't downgrade a chip to a class of chips with fewer pins, or entirely different voltages...

    ...as easily.

    Also, FTFS:

    detect it as a multi-processor graphics card, eliminating the need for SLI setups.

    Should read: "Providing yet another form factor for" SLI setups. (Or crossfire setups, depending on which manufacturer's trademarks you're trading in.)

  • (Score: 2) by takyon on Tuesday May 15 2018, @03:49AM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Tuesday May 15 2018, @03:49AM (#679933) Journal

    Obviously, the way they bond these together is sensitive to defects. Maybe the defects even need to be mirrored for it to work.

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  • (Score: 0) by Anonymous Coward on Tuesday May 15 2018, @11:38AM

    by Anonymous Coward on Tuesday May 15 2018, @11:38AM (#680012)

    In the SLI example given if one die dosen't work you just disable the non-working die. Simlar to how graphics cards currently are sold of lesser versions with less computing cores.

  • (Score: 2) by Grishnakh on Tuesday May 15 2018, @01:06PM

    by Grishnakh (2831) on Tuesday May 15 2018, @01:06PM (#680027)

    one of the stacked wafers does not pass the QA, the entire stack is discarded,

    I don't get it. Why wouldn't they do some preliminary testing on the wafers before stacking them? Then they can discard one if it doesn't pass, or isn't good enough to be rated lower. They'll need to do further testing after stacking of course, since the stacking process could introduce a defect, but with modern automation, the cost of testing should be low.