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posted by Fnord666 on Friday December 14 2018, @01:55AM   Printer-friendly
from the latest-and-greatest dept.

Intel has announced new developments at its Architecture Day 2018:

Sunny Cove, built on 10nm, will come to market in 2019 and offer increased single-threaded performance, new instructions, and 'improved scalability'. Intel went into more detail about the Sunny Cove microarchitecture, which is in the next part of this article. To avoid doubt, Sunny Cove will have AVX-512. We believe that these cores, when paired with Gen11 graphics, will be called Ice Lake.

Willow Cove looks like it will be a 2020 core design, most likely also on 10nm. Intel lists the highlights here as a cache redesign (which might mean L1/L2 adjustments), new transistor optimizations (manufacturing based), and additional security features, likely referring to further enhancements from new classes of side-channel attacks. Golden Cove rounds out the trio, and is firmly in that 2021 segment in the graph. Process node here is a question mark, but we're likely to see it on 10nm and or 7nm. Golden Cove is where Intel adds another slice of the serious pie onto its plate, with an increase in single threaded performance, a focus on AI performance, and potential networking and AI additions to the core design. Security features also look like they get a boost.

Intel says that GT2 Gen11 integrated graphics with 64 execution units will reach 1 teraflops of performance. It compared the graphics solution to previous-generation GT2 graphics with 24 execution units, but did not mention Iris Plus Graphics GT3e, which already reached around 800-900 gigaflops with 48 execution units. The GPU will support Adaptive Sync, which is the standardized version of AMD's FreeSync, enabling variable refresh rates over DisplayPort and reducing screen tearing.

Intel's upcoming discrete graphics cards, planned for release around 2020, will be branded Xe. Xe will cover configurations from integrated and entry-level cards all the way up to datacenter-oriented products.

Like AMD, Intel will also organize cores into "chiplets". But it also announced FOVEROS, a 3D packaging technology that will allow it to mix chips from different process nodes, stack DRAM on top of components, etc. A related development is Intel's demonstration of "hybrid x86" CPUs. Like ARM's big.LITTLE and DynamIQ heterogeneous computing architectures, Intel can combine its large "Core" with smaller Atom cores. In fact, it created a 12mm×12mm×1mm SoC (compare to a dime coin which has a radius of 17.91mm and thickness of 1.35mm) with a single "Sunny Cove" core, four Atom cores, Gen11 graphics, and just 2 mW of standby power draw.

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  • (Score: 0) by Anonymous Coward on Friday December 14 2018, @02:41AM (3 children)

    by Anonymous Coward on Friday December 14 2018, @02:41AM (#774243)

    Why no stats? It just says "single threaded improvement", "new instructions", "improved scalability". That reads more like a wishlist.

  • (Score: 4, Interesting) by driverless on Friday December 14 2018, @06:13AM (2 children)

    by driverless (4770) on Friday December 14 2018, @06:13AM (#774290)

    It's not a wishlist, it's what Intel has been announcing every year now for at least five years, since they ran out of ideas on what to do in their CPUs. A lick of paint here, a minor tweak there, some graphics crap that no-one cares about because Intel can't do graphics to save themselves, and new instructions including IOMAAYXPRT, WSSXPPSSFFTY, and MPLLXNGRT that some guy in Intel's sales department thought up on the toilet this morning, or possibly later in the day, around 4:20. Shit, I've got a ten-year-old Intel quad-core CPU for which the only real differentiating factor from today's CPUs is that it has AES instructions. Which in my case, and most people's cases, are entirely superfluous. There's nothing to announce because they've run out of ideas for what to do.

    • (Score: 0) by Anonymous Coward on Friday December 14 2018, @08:18PM (1 child)

      by Anonymous Coward on Friday December 14 2018, @08:18PM (#774539)

      All the development efforts have been in the [User] Management Engine.

      • (Score: 2) by driverless on Saturday December 15 2018, @12:22AM

        by driverless (4770) on Saturday December 15 2018, @12:22AM (#774619)

        Ah, of course! Those buffer overflows and leaks don't just write themselves.