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Title    TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020
Date    Saturday April 06 2019, @07:33PM
Author    martyb
Topic   
from the when-will-we-need-to-start-miniaturizing-molecules? dept.
https://soylentnews.org/article.pl?sid=19/04/06/148201

takyon writes:

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


Original Submission

Links

  1. "takyon" - https://soylentnews.org/~takyon/
  2. "TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready" - https://www.anandtech.com/show/14175/tsmcs-5nm-euv-process-technology-pdk-drm-eda-tools-3rd-party-ip-ready
  3. "TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020" - https://soylentnews.org/article.pl?sid=18/02/01/0135202
  4. "TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process" - https://soylentnews.org/article.pl?sid=18/05/12/0735217
  5. "TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April" - https://soylentnews.org/article.pl?sid=18/10/10/1912212
  6. "Samsung Plans to Make "5nm" Chips Starting in 2019-2020" - https://soylentnews.org/article.pl?sid=18/07/09/129249
  7. "ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019" - https://soylentnews.org/article.pl?sid=19/01/30/0136241
  8. "Original Submission" - https://soylentnews.org/submit.pl?op=viewsub&subid=32835

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