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TSMC to Build 7nm Process Test Chips in Q1 2018

Accepted submission by takyon at 2017-09-18 22:35:11
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TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a Cache Coherent Interconnect for Accelerators (CCIX), and IP from Cadence (a DDR4 memory controller, PCIe 3.0/4.0 links). Given the presence of the CCIX bus and PCIe 4.0 interconnects, the chip will be used to show the benefits of TSMC's 7 nm process primarily for high-performance compute (HPC) applications. The IC will be taped out in early Q1 2018.

The 7 nm test chips from TSMC will be built mainly to demonstrate capabilities of the semiconductor manufacturing technology for performance-demanding applications and find out more about peculiarities of the process in general. The chip will be based on ARMv8.2 compute cores featuring DynamIQ, as well as a CMN-600 interconnect bus for heterogeneous multi-core CPUs. ARM and TSMC do not disclose which cores they are going to use for the device - the Cortex A55 and A75 are natural suspects, but that's speculation at this point. The new chip will also have a DDR4 memory controller as well as PCI Express 3.0/4.0 links, CCIX bus and peripheral IP buses developed by Cadence. The CCIX bus will be used to connect the chip to Xilinx's Virtex UltraScale+ FPGAs (made using a 16 nm manufacturing technology), so in addition to implementation of its cores using TSMC's 7 nm fabrication process, ARM will also be able to test Cadence's physical implementation of the CCIX bus for accelerators, which is important for future data center products.

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