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takyon [soylentnews.org] writes:

Researchers at MIT, Intel, and ETH Zurich have improved on-package DRAM performance by 33-50% [hpcwire.com] using a new cache management scheme that they call Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation (Banshee):

The researchers developed a new data management scheme relying on a hash function they developed to reduce the metadata burden. Yu and his colleagues' new system, dubbed Banshee, adds three bits of data to each entry in the table. One bit indicates whether the data at that virtual address can be found in the DRAM cache, and the other two indicate its location relative to any other data items with the same hash index.

"In the entry, you need to have the physical address, you need to have the virtual address, and you have some other data," Yu says. "That's already almost 100 bits. So three extra bits is a pretty small overhead."

There's one problem with this approach that Banshee also has to address. If one of a chip's cores pulls a data item into the DRAM cache, the other cores won't know about it. Sending messages to all of a chip's cores every time any one of them updates the cache consumes a good deal of time and bandwidth. So Banshee introduces another small circuit, called a tag buffer, where any given core can record the new location of a data item it caches.

Also at MIT [mit.edu].

Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation [mit.edu] (arXiv [arxiv.org])

Original Submission