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takyon [soylentnews.org] writes:

Gen-Z Interconnect Core Specification 1.0 Published [anandtech.com]

The first major release of the Gen-Z systems interconnect specification is now available [genzconsortium.org]. The Gen-Z Consortium was publicly announced in late 2016 [anandtech.com] and has been developing the technology as an open standard, with several drafts released in 2017 for public comment.

Gen-Z is one of several standards that emerged from the long stagnation of the PCI Express standard after the PCIe 3.0 release. Technologies like Gen-Z, CAPI [anandtech.com], CCIX and NVLink [anandtech.com] seek to offer higher throughput, lower latency and the option of cache coherency, in order to enable much higher performance connections between processors, co-processors/accelerators, and fast storage. Gen-Z in particular has very broad ambitions to blur the lines between a memory bus, processor interconnect, peripheral bus and even straying into networking territory.

The Core Specification released today primarily addresses connecting processors to memory, with the goal of allowing the memory controllers in processors to be media-agnostic: the details of whether the memory is some type of DRAM (eg. DDR4, GDDR6) or a persistent memory like 3D XPoint are handled by a media controller at the memory end of a Gen-Z link, while the processor itself issues simple and generic read and write commands over the link. In this use case, Gen-Z doesn't completely remove the need for traditional on-die memory controllers or the highest-performance solutions like HBM2, but Gen-Z can enable more scalability and flexibility by allowing new memory types to be supported without altering the processor, and by providing access to more banks of memory than can be directly attached to the processor's own memory controller.

Press release [hpcwire.com].

Related: OpenCAPI and Gen-Z [soylentnews.org]

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