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An Anonymous Coward writes:

AMD's first-generation EPYC processor, which is also known by the code name Naples, came with 32 of the company's "Zen" processor cores and 128 PCIe 3.0 lanes (these are used to connect things like storage devices, network interface cards, and accelerators). Naples was composed of four identical chips with eight cores each connected together. Each of those chips was manufactured using GLOBALFOUNDRIES' 14nm technology.

Rome looks like a big upgrade from Naples. The chip consists of 64 of the company's newer "Zen 2" cores and 128 lanes of PCIe 4.0 connectivity.

The chip design also appears to be a radical departure from what AMD delivered with Naples. Instead of stitching together four identical silicon dies on a single package, each with CPU cores, memory controllers, PCIe lanes, and so on, Rome consists of nine individual chips on one package. Eight of those chips consist of CPU cores (and, presumably, their associated cache memory), while the final chip -- known as an input/output (I/O) die -- includes the memory controllers and PCIe lanes.

The CPU dies are manufactured using Taiwan Semiconductor Manufacturing Company's (NYSE:TSM) latest 7nm technology. During a presentation, AMD showed a slide that indicated that the 7nm technology delivers a doubling in density, half the power at identical performance, and greater than 1.25 times the performance at the same power consumption as previous-generation technology. (I checked with AMD, and a spokesman told me that these comparisons were made relative to TSMC's 16nm technology, which was an alternative to the 14nm technology from GLOBALFOUNDRIES that AMD used to build Naples.)

The I/O die, on the other hand, is manufactured on what AMD described in its press release as a "mature 14nm process technology."

This strategy of splitting the chip up into multiple individual chiplets, AMD says, translates into "much higher performance -- more CPU cores at the same power, and more cost-effective manufacture than traditional monolithic chip designs."

https://www.fool.com/investing/2018/11/09/amd-shows-off-rome-data-center-cpu-signs-amazon-as.aspx [fool.com]

The goal of AMD’s event in the middle of the fourth quarter of the year was to put into perspective two elements of AMD’s strategy: firstly, its commitment to delivering a 7nm Vega based product by the end of the year, as the company promised in early 2018, but also to position its 7nm capabilities as some of the best by disclosing the layout of its next generation enterprise processor set to hit shelves in 2019.
[...]
We sat down with AMD’s CTO, Mark Papermaster, to see if we could squeeze some of the finer details about both AMD’s strategy and the finer points of some of the products from the morning sessions.
[...]
IC: Forrest explained on the stage that the datacenter of today is very different to the datacenter ten years ago (or even 3-5 years ago). What decisions are you making today to predict the datacenter of the future?

MP: We believe we will be positioned very well – it all ties back to my opening comments on Moore’s Law. We all accept that the traditional Moore’s Law is slowing down, and that while process does still matter you have to be agile about how you put the pieces together, otherwise you cannot win. We leveraged ourselves to have scalability in our first EPYC launch. We leveraged our ability in our chiplet approach here to combine really small 7nm CPU dies with tried and proven 14nm for the IO die. That modularity only grows in importance going forward. We’ve stated our case as to where we believe it is necessary to keep pace on a traditional Moore’s Law growth despite the slowing of the process gains per node and the length of time between major semiconductor nodes. I think you’ll see others adopt what we’ve done with the chiplet approach, and I can tell you we are committed.
[...]
IC: Where does Rome sit with CCIX support?

MP: We didn’t announce specifically those attributes beyond PCIe 4.0 today, but I can say we are a member of CCIX as we are with Gen Z. Any further detail there you will have to wait until launch. Any specific details about the speeds, feeds, protocols, are coming in 2019.

IC: There have been suggestions that because AMD is saying that Rome is coming in 2019 then that means Q4 2019.

MP: We’re not trying to imply any specific quarter or time frame in 2019. If we look at today’s event, it was timed it to launch our MI60 GPU in 7nm which is imminent. We wanted to really share with the industry how we’ve embraced 7nm, and preview what’s coming out very soon with MI60, and really share our approach on CPU on Zen 2 and Rome. We’re not implying any particular time in 2019, but we’ll be forthcoming with that. Even though the GPU is PCIe 3.0 backwards compatible, it helps for a PCIe 4.0 GPU to have a PCIe 4.0 CPU to connect to!
[...]
IC: One of the key aspects in AMD’s portfolio is the Infinity Fabric, and with Rome you have stated that AMD is now on its second generation IF. Do you see an end in its ability to scale down in process node but also scale out to more chiplets and different IP?

MP: I don’t see an end because the IF is made of both of Scalable Data Fabric and a Scalable Control Fabric. The SCF is the key to giving the modularity and that’s an architectural product. With our SDF we are very confident on the protocols we developed. The SCF protocols are based on the rich history we have with HyperTransport and we are committed in it generationally to improve bandwidth and latency every generation. IF is important when it applies to on chip connectivity, but it can go chip to chip like we did with EPYC, and also with Vega Radeon Instinct in connecting GPU to GPU. For the chip to chip IF, you are also dependent on the package technology. We see tremendous improvements in package technology over the next five years.

Original Submission