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takyon [soylentnews.org] writes:

Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510 [anandtech.com]

It's that time of the year again, and after last month's unveiling of Arm's newest infrastructure Neoverse V1 and Neoverse N2 CPU IPs, it's now time to cover the client and mobile side of things. This year, things Arm is shaking things up quite a bit more than usual as we're seeing new three new generation microarchitectures for mobile and client: The flagship Cortex-X2 core, a new A78 successor in the form of the Cortex-A710, and for the first time in years, a brand-new little core with the new Cortex-A510. The three new CPUs form a new trio of Armv9 compatible designs that aim to mark a larger architectural/ISA shift that comes very seldomly in the industry.

Alongside the new CPU cores, we're also seeing a new L3 and cluster design with the DSU-110, and Arm is also making a big upgrade in its interconnect IP with the new cache coherent CI-700 mesh network and NI-700 network-on-chip IPs.

The Cortex-X2, A710 and A510 follow up on last year's X1, A78 and A55. For the new Cortex-X2 and A710 in particular, these are direct microarchitectural successors to their predecessors. These parts, while iterating on generational improvements in IPC and efficiency, also incorporate brand-new architectural features in the form of Armv9 and new extensions such as SVE2.

The Cortex-X2 is a large, power-hungry core. Arm is claiming +16% more integer performance than its predecessor, when comparing a design with double the L3 cache (8 MB instead of 4 MB with Cortex-X1 [wikipedia.org]). The improvement may not be realized in next year's smartphones due to thermal issues.

The Cortex-A710 can improve performance by 10% at the same power usage, or use 30% less power than the Cortex-A78 [wikipedia.org] while delivering the same performance. This may be dependent on the L3 cache since Arm compares A710 with 8MB to A78 with 4MB, and SoC designers may choose to stick with 4 MB. The A710 will be the only core of the trio to retain 32-bit (AArch32) support, in order to give the Chinese market more time to shift to 64-bit only applications, because it "lacks the homogeneous ecosystem capabilities of the global Play Store markets".

The Cortex-A510 is Arm's long-awaited update to the Cortex-A55 [wikipedia.org], which was launched in 2017. It employs a "merged-core architecture", similar to AMD's maligned Bulldozer microarchitecture [wikipedia.org], except only the FP/SIMD back-end and L2 cache are shared between core pairs. Using pairs of merged A510 cores in a design is actually optional, but would be expected due to the smaller die size it can achieve. Arm's graph comparing performance and power usage for the A510 and A55 [anandtech.com] show that performance and efficiency is nearly identical until they reach higher frequencies, where the A510 pulls ahead by using 20% less power or having 10% more performance at some point.

See also: Arm Announces Armv9 Architecture: SVE2, Security, and the Next Decade [anandtech.com]

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