SoylentNews

upstart [soylentnews.org] writes:

████ # This file was generated bot-o-matically! Edit at your own risk. ████

OpenPOWER Foundation | Libre-SOC 180nm Power ISA ASIC Submitted to Imec for Fabrication [openpowerfoundation.org]:

Blogs

Libre-SOC [libre-soc.org]‘s 180nm Power ISA Test ASIC, developed in conjunction with Chips4Makers [chips4makers.io] and Sorbonne Université’s LIP6 [lip6.fr], has been submitted to Imec [imec-int.com]’s MPW Shuttle Service for fabrication in TSMC [tsmc.com] 180nm.

The team that collaborated on the project has a wealth of expertise in software engineering and ethical hardware design, and as a matter of principle used a fully free and open source toolchain to deliver this groundbreaking chip. This makes it the first ASIC of its kind, with many more to come – each edging closer to an attractive open hardware alternative to current proprietary offerings. The project was funded by NLnet Foundation [nlnet.nl] as part of its Next Generation Internet initiative, as a fundamental technological building block that will help increase privacy and trustworthiness for end users.

Implementing a fixed-point subset of the v3.0B OpenPOWER ISA, Libre-SOC’s 180nm Power ISA Test ASIC is the world’s first Power ISA implementation designed outside of IBM to go to silicon, following IBM’s open sourcing of the POWER ISA in 2019 [ibm.com]. Libre-SOC used Microwatt, which was designed by IBM and sent to Skywater for fabrication earlier this year [openpowerfoundation.org], as a reference design for benchmarking and cross-verification.

The ASIC is 130,000 gates, measures 5.5 x 5.9 mm^2, contains four 4k SRAMs developed by Chips4Makers, and a 300 mhz Voltage-Controlled PLL developed by Professor Galayko [lip6.fr]of Sorbonne Université. The VLSI tape-out was carried out by Jean-Paul Chaput [lip6.fr] of Sorbonne Université using coriolis2, and the Static Timing Analysis and LVS checking by Dr. Marie-Minerve Louërat [lip6.fr] of Sorbonne Université. The HDL of the core is entirely in nmigen, a python Object-Orientated HDL.

The Cell Library used, FlexLib, also sponsored by NLnet, was developed by Staf Verhaegen [linkedin.com] of Chips4Makers, and is Libre-Licensed. Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout: an important requirement to fulfil their transparency obligations to NLnet under the Privacy and Enhanced Trust Programme.

LIP6 developed the VLSI ASIC Layout tool, coriolis2. Coriolis2 is also entirely Libre-licensed and is a fully automated HDL to GDS-II tool which requires no manual intervention. It is independent of OpenLANE, is developed entirely in Europe, and has the same fully automated capability of turning HDL into 100% DRC clean GDS-II.

LIP6 were able to create the GDS-II tape-out under NDA using “Real” (non-symbolic) versions of Chips4Makers’ FlexLib, whilst Libre-SOC developers assisted using Symbolic Cells.

“We developed this ASIC on the Power architecture because of its supercomputing pedigree, and the decades-long commitment and stability that IBM and other OpenPOWER Foundation members have sustained,” said Luke Kenneth Casson Leighton [libre-soc.org], lead developer and project coordinator for Libre-SOC. “On this strong base, we can build a reliable, efficient Hybrid 3D CPU-VPU-GPU, and our next test ASIC will include Draft Cray-style Vector Extensions, SVP64.”

For more information, contact the developers of Libre-SOC at http://libre-soc.org [libre-soc.org].

Original Submission