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Arthur T Knackerbracket [soylentnews.org] writes:

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Arthur T Knackerbracket has processed the following story [tomshardware.com]:

Insufficient packaging capacity is to blame.

The chairman of TSMC admitted that the ongoing short supply of compute GPUs for artificial intelligence (AI) and high-performance computing (HPC) applications is caused by constraints of its chip-on-wafer-on-substrate (CoWoS) packaging capacity. This shortage is expected to persist for around 18 months due to rising demand for generative AI applicationsand relatively slow expansion of CoWoS capacity at TSMC.  

"It is not the shortage of AI chips, it is the shortage of our CoWoS capacity," said Mark Liu, the chairman of TSMC, in a conversation with Nikkei [nikkei.com] at Semicon Taiwan. "Currently, we cannot fulfill 100% of our customers' needs, but we try to support about 80%. We think this is a temporary phenomenon. After our expansion of [advanced chip packaging capacity], it should be alleviated in one and a half years."

TSMC is the producer of the majority of AI processors, including Nvidia's A100 and H100 compute GPUs that are integral to AI tools like ChatGPT and are predominantly used in AI data centers. These processors, just like solutions from other players like AMD, AWS, and Google, use HBM memory (which is essential for high bandwidth and proper functioning of extensive AI language models) and CoWoS packaging, which puts additional strain on TSMC's advanced packaging facilities.

Liu said that demand for CoWoS surged unexpectedly earlier this year, tripling year-over-year, leading to the current supply constraints. TSMC recognizes that demand for generative AI services is growing and so is demand for appropriate hardware, so it is speeding up expansion of CoWoS capacity to meet demand for compute GPUs as well as specialized AI accelerators and processors.

At present, the company is installing additional tools for CoWoS at its existing advanced packaging facilities, but this takes time and the company expects its CoWoS capacity to double only by the end of 2024.

In addition, TSMC recently announced intention to invest $2.9 billion in a new facility dedicated to advanced chip packaging. This facility, located near Miaoli, Taiwan, is a testament to the company's commitment to addressing demand for advanced packaging from all sectors and recognized importance of advanced chip packaging in the semiconductor industry going forward

This focus on advanced chip packaging is not exclusive to TSMC; other industry giants like Intel and Samsung are also prioritizing it, with Intel aiming to quadruple its capacity for its top-tier chip packaging by 2025. Traditional outsource semiconductor assembly and test (OSAT) companies like ASE and Amkor also have technologies similar to CoWoS, but they yet have to build up capacity for them comparable to that of TSMC, Intel, and Samsung.

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Arthur T Knackerbracket has processed the following story [theregister.com]:

Bad news for anyone looking to get their hands on Nvidia's top specced GPUs, such as the A100 or H100: it's not going to get any easier to source the parts until at least the end of 2024, TSMC has warned.

The problem, it seems, isn't that TSMC – which fabricates not just those GPUs for Nvidia but also components for AMD, Apple, and many others – can't make enough chips. Rather, a lack of advanced packaging capacity used to stitch the silicon together is holding up production, TSMC chairman Mark Liu told Nikkei Asia [nikkei.com].

According to Liu, TSMC is only able to meet about 80 percent of demand for its chip on wafer on substrate (CoWoS) packaging technology. This is used in some of the most advanced chips on the market today – particularly those that rely on high-bandwidth memory (HBM) which is ideal for AI workloads.

Liu expects this is a temporary bottleneck in the production of machine-learning accelerators and that additional CoWoS capacity should come online within a year and a half. Incidentally, TSMC recently announced plans to expand [theregister.com] its advanced packaging capacity in Taiwan with a $3 billion facility at the Tongluo Science Park in Miaoli County.

Until TSMC can bring additional capacity online, Nvidia's H100 and older A100 – which power many popular generative AI models, such as GPT-4 – are at the heart of this shortage. However, it's not just Nvidia. AMD's upcoming Instinct MI300-series accelerators – which it showed off [theregister.com] during its Datacenter and AI event in June – make extensive use of CoWoS packaging technology.

AMD's MI300A APU is currently sampling with customers and is slated to power [nextplatform.com] Lawrence Livermore National Laboratory's El Capitan system, while the MI300X GPU is due to start making its way into customers' hands in Q3.

We've reached out to AMD for comment on whether the shortage of CoWoS packaging capacity could impact availability of the chip and we'll let you know if we hear anything back.

It's worth noting that TSMC's CoWoS isn't the only packaging tech out there. Samsung, which is rumored [bloomberg.com] to pick up some of the slack for the production of Nvidia GPUs, has I-Cube and H-Cube for 2.5D packaging and X-Cube for 3D packaging.

Intel, meanwhile, packages several of the chiplets used in its Ponte Vecchio GPU Max [theregister.com] cards, but doesn't rely on CoWoS tech to stitch them together. Chipzilla has developed its own advanced packaging tech, which can work with chips from different fabs or process nodes. It's called embedded multi-die interconnect bridge (EMIB) for 2.5D packaging and Foveros for vertically stacking chiplets on top of one another. ®

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