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Arthur T Knackerbracket [soylentnews.org] writes:

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Arthur T Knackerbracket has processed the following story [techspot.com]:

Last week, Applied Materials pulled back the curtain on its latest materials engineering solutions designed to enable copper wiring to scale down to 2nm dimensions and below while also reducing electrical resistance and strengthening chips for 3D stacking.

The company's Black Diamond low-k dielectric material has been offered since the early 2000s. It surrounds copper wires with a special film engineered to reduce the buildup of electrical charges that increase power consumption and cause interference between electrical signals.

Applied Materials has now come up [appliedmaterials.com] with an enhanced version of Black Diamond, which reduces the minimum k-value even further, enabling copper wiring scaling to the 2nm node while also increasing mechanical strength – a critical property as chipmakers look to stack multiple logic and memory dies vertically.

But scaling the copper wiring itself as dimensions shrink is another enormous challenge. Today's most cutting-edge logic chips can pack over 60 miles of copper wires that are fashioned by first etching trenches into the dielectric material and then depositing an ultra-thin barrier layer to prevent copper migration. A liner layer goes down next to aid copper adhesion before the final copper deposition fills the remaining space.

The problem is that at 2nm dimensions and below, the barrier and liner layers consume an increasingly large percentage of the available trench volume, leaving little room for sufficient copper fill and risking high resistance and reliability issues. Applied Materials has solved this predicament with this brand-new materials concoction.

Their latest Integrated Materials Solution (IMS) combines six different core technologies into one high-vacuum system, including an industry-first pairing of ruthenium and cobalt to form an ultra-thin 2nm binary metal liner. This allows a 33% reduction in liner thickness compared to previous generations while also improving surface properties for seamless, void-free copper adhesion and reflow. The end result is up to 25% lower electrical resistance in chip wiring to boost performance and reduce power leakage.

Applied Materials claims that all leading logic chipmakers have already adopted its new copper barrier seed IMS with ruthenium CVD technology for 3nm chip production, with 2nm nodes expected to follow.

The company also estimates its total served available market for chip wiring solutions will swell from around $6 billion per 100,000 wafers starting today to over $7 billion with the introduction of backside power delivery schemes.

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