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Intel Skylake Desktop Chips Launch (draft)

Accepted submission by takyon at 2015-08-05 18:05:21
Hardware []

When the processors are set at 3 GHz, Anandtech benchmarking showed 2-3% instructions per clock (IPC) improvement over Broadwell, and over 5% IPC improvement from Haswell to Skylake (a comparison they justified by calling Broadwell on the desktop "a niche focused launch"). Skylake's overclocking potential seems better than Haswell and Broadwell. One explanation is that the fully integrated voltage regulator has been removed.

Discrete gaming performance decreased versus Haswell when both CPUs were limited to 3 GHz:

Discrete graphics card performance decreases on Skylake over Haswell.

This doesn't particularly make much sense at first glance. Here we have a processor with a higher IPC than Haswell but it performs worse in both DDR3 and DDR4 modes. The amount by which it performs worse is actually relatively minor, usually -3% with the odd benchmark (GRID on R7 240) going as low as -5%. Why does this happen at all?

So we passed our results on to Intel, as well as a few respected colleagues in the industry, all of whom were quite surprised. During a benchmark, the CPU performs tasks and directs memory transfers through the PCIe bus and vice versa. Technically, the CPU tasks should complete quicker due to the IPC and the improved threading topology, so that only leaves the PCIe to DRAM via CPU transfers.

Our best guess, until we get to IDF to analyze what has been changed or a direct explanation from Intel, is that part of the FIFO buffer arrangement between the CPU and PCIe might have changed with a hint of additional latency. That being said, a minor increase in PCIe overhead (or a decrease in latency/bandwidth) should be masked by the workload, so there might be something more fundamental at play, such as bus requests being accidentally duplicated or resent due to signal breakdown. There might also be a tertiary answer of an internal bus not running at full speed.

Skylake processors will support both DDR3L and DDR4 memory.

In the lead up to the launch of Intel's Skylake platform, architecture details have been both thin on the ground and thin in the air, even when it comes down to fundamental details about the EU counts of the integrated graphics, or explanations regarding the change in processor naming scheme. In almost all circumstances, we've been told to wait until Intel's Developer Forum in mid-August for the main reason that the launch today is not the full stack Skylake launch, which will take place later in the quarter.

Mobile Skylake will be the processors to watch.,4252.html []

Original Submission