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posted by martyb on Wednesday November 07 2018, @04:49AM   Printer-friendly
from the moah-powah dept.

AMD has announced the next generation of its Epyc server processors, with up to 64 cores (128 threads) each. Instead of an 8-core "core complex" (CCX), AMD's 64-core chips will feature 8 "chiplets" with 8 cores each:

AMD on Tuesday formally announced its next-generation EPYC processor code-named Rome. The new server CPU will feature up to 64 cores featuring the Zen 2 microarchitecture, thus providing at least two times higher performance per socket than existing EPYC chips.

As discussed in a separate story covering AMD's new 'chiplet' design approach, AMD EPYC 'Rome' processor will carry multiple CPU chiplets manufactured using TSMC's 7 nm fabrication process as well as an I/O die produced at a 14 nm node. As it appears, high-performance 'Rome' processors will use eight CPU chiplets offering 64 x86 cores in total.

Why chiplets?

Separating CPU chiplets from the I/O die has its advantages because it enables AMD to make the CPU chiplets smaller as physical interfaces (such as DRAM and Infinity Fabric) do not scale that well with shrinks of process technology. Therefore, instead of making CPU chiplets bigger and more expensive to manufacture, AMD decided to incorporate DRAM and some other I/O into a separate chip. Besides lower costs, the added benefit that AMD is going to enjoy with its 7 nm chiplets is ability to easier[sic] bin new chips for needed clocks and power, which is something that is hard to estimate in case of servers.

AMD also announced that Zen 4 is under development. It could be made on a "5nm" node, although that is speculation. The Zen 3 microarchitecture will be made on TSMC's N7+ process ("7nm" with more extensive use of extreme ultraviolet lithography).

AMD's Epyc CPUs will now be offered on Amazon Web Services.

AnandTech live blog of New Horizon event.

Previously: AMD Epyc 7000-Series Launched With Up to 32 Cores
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 48-core Xeons Using Multiple Dies, Ahead of AMD Announcement

Related: Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
Oracle Offers Servers with AMD's Epyc to its Cloud Customers

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  • (Score: 4, Informative) by takyon on Wednesday November 07 2018, @07:05AM (2 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday November 07 2018, @07:05AM (#758861) Journal

    AMD's CEO Lisa Su used to be Director of Emerging Products at IBM.

    Ryzen uses simultaneous multithreading [], which was developed at IBM way back in 1968.

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  • (Score: 0) by Anonymous Coward on Wednesday November 07 2018, @07:23AM (1 child)

    by Anonymous Coward on Wednesday November 07 2018, @07:23AM (#758867)

    Yup everything old is new again.

    Now if INTEL and AMD will get multiple byte (256 to 32k) in a single instruction charged with a single clock "tick". That was nice of earlier IBM ASM. Reality it was microcode running a loop, but it was set up and ran ran as single assembly instruction (like MV(255) from,to compiled up to 6 total bytes (4 bytes if reg to reg pointing). Allowed for every tight code size and simple to read. When I started it 64kB was largest a program coude compile to, but on some of my ealry machines (System 3) we had 12kB of total storage.

    • (Score: 2, Funny) by Anonymous Coward on Wednesday November 07 2018, @12:40PM

      by Anonymous Coward on Wednesday November 07 2018, @12:40PM (#758929)

      Yup everything old is new again.

      I wanna be new again [sigh]