Intel is talking about improvements it has made to transistor scaling [arstechnica.com] for the 10nm process node, and claims that its version of 10nm will increase transistor density by 2.7x rather than doubling it.
On the face of it, three years between process shrinks, rather than the traditional two years, would appear to end Moore's Law. But Intel claims that's not so. The company says that the 14nm and 10nm process shrinks in particular more than doubled the transistor density. At 10nm, for example, the company names a couple of techniques that are enabling this "hyperscaling." Each logic cell (an arrangement of transistors to form a specific logic gate, such as a NAND gate or a flip flop) is surrounded by dummy gates: spacers to isolate one cell from its neighbor. Traditionally, two dummy gates have been used at the boundary of each cell; at 10nm, Intel is reducing this to a single dummy gate, thereby reducing the space occupied by each cell and allowing them to be packed more tightly.
Each gate has a number of contacts used to join them to the metal layers of the chip. Traditionally, the contact was offset from the gate. At 10nm, Intel is stacking the contacts on top of the gates, which it calls "contact over active gate." Again, this reduces the space each gate takes, increasing the transistor density.
Intel proposes a new metric for measuring transistor density:
Intel wants to describe processes in terms of millions of logic transistors per square millimeter, calculated using a 3:2 mix of NAND cells and scan flip flop cells. Using this metric, the company's 22nm process managed 15.3 megatransistors per millimeter squared (MTr/mm2). The current 14nm process is 37.5MTr/mm2, and at 10nm, the company will hit 100.8MTr/mm2. Competing 14nm/16nm processes only offer around 28MTr/mm2, and Intel estimates that competing 10nm processes will come in at around 50MTr/mm2.
See also: the International Roadmap for Devices and Systems [hpcwire.com].