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TSMC "5nm", "3nm", Stacked Silicon, and More

Accepted submission by takyon at 2020-08-28 10:37:40

TSMC announced a number of node scaling details and technological advancements at its 2020 Technology Symposium:

TSMC's first "5nm" node (N5) has a lower defect rate [] than its initial "7nm" node did at the same point in its development cycle (high volume manufacturing, which N5 is now in). This is due in part to increasing use of extreme ultraviolet lithography [] (EUV). "5nm" will represent 11% of TSMC's sub-"16nm" wafer production [] in 2020.

TSMC's "3nm" node [] (N3) will continue to use FinFETs rather than gate-all-around (GAA) transistors [], and is scheduled for volume production in mid-late 2022. Performance is expected to improve 10-15% at the same power (compared to N5), or power consumption will be reduced 25-30% for the same performance. Logic area density improvement will be 1.7x, but SRAM [] density will only increase by 1.2x, leading to a 1.27x overall density increase for chips that are 70% SRAM and 30% logic.

Intel's EMIB [] (Embedded Die Interconnect Bridge) connects "chiplets" together without using a full silicon interposer. TSMC has its own version that it is calling Local Si Interconnect [] (LSI), and it will be used with other packaging technologies. TSMC has demonstrated 12-layer stacking of chips [] using through silicon vias (TSVs), although cooling or doing anything useful with them could be somebody else's job.

See also: TSMC Updates on Node Availability Beyond Logic: Analog, HV, Sensors, RF []
TSMC Launches New N12e Process: FinFET at 0.4V for IoT []
2023 Interposers: TSMC Hints at 3400mm2 + 12x HBM in one Package []
TSMC and Graphcore Prepare for AI Acceleration on 3nm []
TSMC Has Reportedly Secured Orders for Its 2nm Node – Samsung May Not Beat Its Foundry Rival Until 2030, Claims New Report []

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