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posted by martyb on Monday October 02 2017, @08:08PM   Printer-friendly
from the how-many-atoms-wide-is-that? dept.

GlobalFoundries: Next-generation chip factories will cost at least $10 billion

The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost between $10 billion and $12 billion to build a next-generation chip factory based on the latest technology, dubbed 7-nanometer production. And one for the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.

There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factory.

Dean Takahashi from VentureBeat interviewed Sanjay Jha, CEO of GlobalFoundries:

Basically, the numbers don't mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don't know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It's not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.

What has happened, as the line widths get closer, it's getting harder and harder to get incremental performance. You can get scale that you want, but getting performance is harder. You can get some power consumption reduction, as well. With 14nm, most people use .8. At 10nm, most people are using .7. As you go, there's a clear scaling with the ratio of the squares of those two numbers. That gives you about 20-25 percent reduction in power consumption. So we deliver performance, some power consumption reduction, and scaling.

[...] VB: Going back to where the specs are on nanometers, how do customers view the problem of figuring out who's really ahead of the game as far as manufacturing?

Jha: They look at four things. They look at density, performance, power consumption, and cost. We call it PPAC. That's what most customers care about. They don't care about 12nm or 10nm. Even if the density of 12nm is a little lower than 10nm, if the complexity of the process is lower and the cost is lower and the power consumption may be lower, that may allow them to go after the mobile space a little better than 10nm. They look at the PPAC and target it to particular models.

Rock's law.

Related: AMD, GlobalFoundries Renew Vows, Focus on Path to 7nm
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
AMD Expected to Release Ryzen CPUs on a 12nm Process in Q1 2018

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  • (Score: 2) by Scrutinizer on Monday October 02 2017, @10:24PM (8 children)

    by Scrutinizer (6534) on Monday October 02 2017, @10:24PM (#576264)

    I'm still waiting for chip technology to make the jump into the third dimension. We have crazy sci-fi semiconductor technology [] at our fingertips, if perhaps not within our grasp, that may help to facilitate such a change.


    I have just discovered that the diamond crystal wafers made possible by chemical vapor deposition seem to be downplayed or omitted by the new owner of the patents in favor of OOH SHINY jewelry. Perhaps our new diamond-powered AI overlords will have to wait another ~14 years until the patents expire...

    • (Score: 3, Informative) by mhajicek on Monday October 02 2017, @10:35PM (3 children)

      by mhajicek (51) on Monday October 02 2017, @10:35PM (#576272)

      Stacking chips makes thermal dissipation difficult.

      The spacelike surfaces of time foliations can have a cusp at the surface of discontinuity. - P. Hajicek
      • (Score: 0) by Anonymous Coward on Monday October 02 2017, @11:21PM (1 child)

        by Anonymous Coward on Monday October 02 2017, @11:21PM (#576299)

        Quite true. The thermal resiliency of diamond semiconductors (as compared to silicon-based versions) is hoped to allow more leeway in dealing with the heat problem. I think I'd be happy with a monstrosity of a chip layered with built-in heat pipes between each section, particularly after I finish my move to northern Alaska...

      • (Score: 2) by JoeMerchant on Tuesday October 03 2017, @12:33PM

        by JoeMerchant (3937) on Tuesday October 03 2017, @12:33PM (#576552)

        True, though with the consistent reductions in thermal output (per gate), do we really need to keep the traces so close to each other? Sure: use a 5nm process, but space the traces at 20nm (6% density) and then stack them 16 layers deep for a net 1.25nm spacing - the space between could include vertical heat pipes.

        New ideas, new processes, risk. Why take risks when you can invest $20B to net $100B in 5 years time?

        🌻🌻 []
    • (Score: 2) by takyon on Tuesday October 03 2017, @12:30AM

      by takyon (881) <> on Tuesday October 03 2017, @12:30AM (#576326) Journal
    • (Score: 2) by tibman on Tuesday October 03 2017, @12:39AM (1 child)

      by tibman (134) Subscriber Badge on Tuesday October 03 2017, @12:39AM (#576330)

      This is the closest thing i've seen in production: []

      SN won't survive on lurkers alone. Write comments.
      • (Score: 2) by JoeMerchant on Tuesday October 03 2017, @01:47PM

        by JoeMerchant (3937) on Tuesday October 03 2017, @01:47PM (#576577)

        With process density so high, I don't understand why we haven't started seeing high capacity integrated RAM (presumably very high speed) on-die with the processor.

        🌻🌻 []
    • (Score: 2) by TheRaven on Tuesday October 03 2017, @08:51AM

      by TheRaven (270) on Tuesday October 03 2017, @08:51AM (#576499) Journal
      Here's the problem: Moore's law is still here, but Dennard Scaling isn't. We're still getting double the number of transistors per dollar every couple of years, but we're not getting the reduction in power consumption per transistor. You double the number of transistors, you (almost) double the power consumption. Going 3D doesn't help with this, if anything it makes it worse, because dissipating the heat from the middle is a lot harder.
      sudo mod me up