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posted by n1 on Tuesday June 06 2017, @04:11AM   Printer-friendly
from the good-things,-small-packages dept.

IBM, which demonstrated the world's first 7nm process silicon chip in 2015, has followed up at the 5nm node. Extreme ultraviolet lithography was required:

IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography.

GAAFETs are the next evolution of tri-gate finFETs: finFETs, which are currently used for most 22nm-and-below chip designs, will probably run out of steam at around 7nm; GAAFETs may go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.

[...] One major advantage of IBM's 5nm GAAFETs is a significant reduction in patterning complexity. Ever since we crossed the 28nm node, chips have become increasingly expensive to manufacture, due to the added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the multi-stage process where the layout of the chip—defining where the nanosheets and other components will eventually be built—is etched using a lithographic process. As features get smaller and more complex, more patterning stages are required, which drives up the cost and time of producing each wafer.

[...] IBM says that, compared to commercial 10nm chips (presumably Samsung's 10nm process), the new 5nm tech offers a 40 percent performance boost at the same power, or a 75 percent drop in power consumption at the same performance. Density is also through the roof, with IBM claiming it can squeeze up to 30 billion transistors onto a 50-square-millimetre chip (roughly the size of a fingernail), up from 20 billion transistors on a similarly-sized 7nm chip.

Press release. Also at The Verge, TechCrunch, EE Times, PCMag, and CNET.

Related:
Samsung Plans a "4nm" Process


Original Submission

Related Stories

IBM and Partners Develop 7nm Process Chips 10 comments

Numerous sources are reporting that IBM's recent $3 billion investment in new chipmaking technologies and collaboration with the State University of New York in Albany, GlobalFoundries, and Samsung Electronics Co. is beginning to bear fruit. IBM has developed chips with functional transistors using a 7 nanometer process technology.

In particular, silicon-germanium (SiGe) has been incorporated into FinFET transistors, the fins of which are stacked at a pitch of less than 30nm, compared to a 42nm pitch for Intel's 14nm Broadwell chips. Long delayed extreme ultraviolet (EUV) lithography from ASML was used to etch the features. Although ASML's EUV tools are still slower and more expensive than conventional lithography, Michael Liehr, the executive vice president for innovation and technology at the SUNY Poly research center, predicted that ASML would improve EUV over the next four to six years, before 7nm chips are set to reach the market. More aggressive estimates put the introduction of 7nm chips around 2017-2018.

Ars Technica has a story on this topic with more technical background.


Original Submission

Samsung Plans a "4nm" Process 12 comments

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.

Source.

But how many transistors per square millimeter is it?


Original Submission

GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm 9 comments

GlobalFoundries: Next-generation chip factories will cost at least $10 billion

The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost between $10 billion and $12 billion to build a next-generation chip factory based on the latest technology, dubbed 7-nanometer production. And one for the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.

There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factory.

Dean Takahashi from VentureBeat interviewed Sanjay Jha, CEO of GlobalFoundries:

Basically, the numbers don't mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don't know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It's not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.

"3nm" Test Chip Taped Out by Imec and Cadence 13 comments

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes 10 comments

Samsung has replaced planned "6nm" and "5nm" nodes with a new "5nm" node on its roadmap, and plans to continue scaling down to "3nm", which will use gate-all-around transistors instead of Fin Field-effect transistors. Extreme ultraviolet lithography (EUV) will be required for everything below "7nm" (TSMC and GlobalFoundries will start producing "7nm" chips without EUV initially):

Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to "allow greater area scaling and ultra-low power benefits" when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.

[...] Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.

[...] The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung's own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.

MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung's fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the[sic] EUV in general will have a clear impact on Samsung's technologies several years down the road.

Previously: Samsung Plans a "4nm" Process

Related: IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process


Original Submission

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  • (Score: 0) by Anonymous Coward on Tuesday June 06 2017, @05:19AM (6 children)

    by Anonymous Coward on Tuesday June 06 2017, @05:19AM (#521180)

    But what does this chip do?

    • (Score: 2) by takyon on Tuesday June 06 2017, @05:23AM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday June 06 2017, @05:23AM (#521183) Journal

      It destroys jobs.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    • (Score: 2) by bob_super on Tuesday June 06 2017, @06:54AM (2 children)

      by bob_super (1357) on Tuesday June 06 2017, @06:54AM (#521206)

      Lets you watch cat pictures on FB for an extra 5 minutes, before your 4K 6-inch screen finishes the battery.

      • (Score: 0) by Anonymous Coward on Tuesday June 06 2017, @08:05AM

        by Anonymous Coward on Tuesday June 06 2017, @08:05AM (#521225)

        Ah, I see you're getting the new Galaxy Note 8 [knowyourmobile.com].

      • (Score: 0) by Anonymous Coward on Tuesday June 06 2017, @08:05AM

        by Anonymous Coward on Tuesday June 06 2017, @08:05AM (#521226)

        Ah, I see you're getting the new Galaxy Note 8 [knowyourmobile.com].

    • (Score: 0) by Anonymous Coward on Tuesday June 06 2017, @07:46AM

      by Anonymous Coward on Tuesday June 06 2017, @07:46AM (#521217)

      But what does this chip do?

      It figures out how to make chips with even smaller transistors.

    • (Score: 2) by bzipitidoo on Tuesday June 06 2017, @02:54PM

      by bzipitidoo (4388) Subscriber Badge on Tuesday June 06 2017, @02:54PM (#521341) Journal

      Makes 7nm chips dirt cheap-- Raspberry Pi cheap.

  • (Score: 0) by Anonymous Coward on Tuesday June 06 2017, @06:09AM (1 child)

    by Anonymous Coward on Tuesday June 06 2017, @06:09AM (#521198)

    The atomic radius of a single silicon atom is 0.111 nm. At 3 nm and below your minimum feature size is only a couple dozen atoms or so across.

  • (Score: 2) by richtopia on Tuesday June 06 2017, @04:34PM

    by richtopia (3160) Subscriber Badge on Tuesday June 06 2017, @04:34PM (#521403) Homepage Journal

    Those scanning electron micrographs of the chip boggle the mind: it looks like IBM is digging out from under their silicon nanosheets and filling the gap with high-k metal gates. I don't know how you would go about that: these structures are indeed tiny but gravity still affects them. Not to mention etching below an existing layer.

    I'm curious how involved Samsung and GF were in these chips. Now that IBM is fabless I would assume that GF actually manufactured the chip, but Samsung's level of involvement is a bit of a mystery to me.

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