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posted by janrinok on Sunday May 13 2018, @08:14AM   Printer-friendly

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020

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  • (Score: 4, Informative) by takyon on Sunday May 13 2018, @04:07PM

    by takyon (881) <> on Sunday May 13 2018, @04:07PM (#679214) Journal

    the performance-efficiency gains are not so impressive...

    I disagree. I think the results are impressive. They just aren't "free lunch", "Ghost of Moore's Past" impressive. But not many things in life can just get a 10-20% improvement repeatedly, like semiconductor manufacturing can. The 1.8x density increase is a bigger deal and allows you to make more compact chips (for devices like smartwatches, smartglasses, phone/VR SoCs, whatever) or increase the number of cores, and as we know performance can sometimes scale up with the number of cores. If the number of CPU cores isn't increased, it can allow integrated graphics to be expanded again.

    Or is it more likely that's about as good as this particular configuration will get, barring fine adjustments?

    We still haven't switched to something more exotic like carbon nanotube transistors, or Silicon-Germanium, or tunnel field-effect transistors [].

    Companies still see paths down to below 5nm or even 3nm: []

    It’s even possible that today’s technology and its future iterations may provide enough performance beyond 5nm. Today’s leading-edge transistor type—the finFET—will likely extend to 5nm or 3nm, depending on how the nodes are defined. Then, at 4nm/3nm, some are moving toward a next-generation transistor technology called gate-all-around FETs, where a finFET is placed on its side and a gate is wrapped around it.

    [...] But there is also a chance the industry will require new and faster devices beyond gate-all-around. [...] So in R&D, the industry is working on several technologies for 2.5nm and 1.5nm. At those nodes, the industry could go down the following paths:

    • Extend gate-all-around FETs or develop more complex versions of the technology, such as complementary FETs (CFETs) and vertical nanowire FETs.
    • Take existing finFETs and tweak them with new materials, creating what’s called a negative-capacitance FET (NC-FET).
    • Integrate devices into an advanced package.

    Here's an article about gate-all-around transistors [] from IBM.

    Part of the problem is that even if you can build at a tiny node, it isn't necessarily economical. Scaling has been slowed down, primarily to give more time for extreme ultraviolet lithography (EUV) to mature. At this point, it will probably gain traction at the 7nm node, with EUV used on only certain layers at first, and then the whole process later on.

    If traditional transistor types (to include stuff like gate-all-around), run out of steam, or we get as close to the atomic limits as possible, then we'll have a period of stagnation that will actually be good for everybody, because it will give us (big companies and startups) a chance to explore new approaches like the aforementioned nanotubes, etc. As long as it was possible to increase density and performance with slight adjustments, alternatives aren't fully and rapidly explored.

    One obvious path to more performance is to vertically stack transistors/cores. As long as your use case can tolerate an extreme emphasis on parallelism (such as graphics, multithreaded code, machine learning, etc.), then you can benefit from vertical stacking. Apparently, this may be coming soon with a technology referred to as "Wafer-on-Wafer" [], which seems like a quick and dirty way to double performance.

    I will also submit the following story about Intel throwing money at a bunch of startups so that it doesn't become irrelevant: []

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