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takyon [soylentnews.org] writes:

Cadence and Micron Demo DDR5-4400 IMC and Memory, Due in 2019 [anandtech.com]

Cadence this week introduced the industry's first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence's IP and test chip [are] fabricated using TSMC's 7 nm process technology, and is designed to enable SoC developers to begin on their DDR5 memory subsystems now and get them to market in 2019-2020, depending on high-volume DDR5 availability. At a special event, Cadence teamed up with Micron to demonstrate their DDR5 DRAM subsystem. In the meantime, Micron has started to sample its preliminary DDR5 chips to interested parties.

Cadence's DDR5 memory controller and PHY achieve a 4400 MT/s data rate with CL42 using Micron's prototype 8 Gb DDR5 memory chips. Compared to DDR4 today, the supply voltage of DDR5 is dropped from 1.2 volts to 1.1 volts, with an allowable fluctuation range of only ±0.033 V. In this case, the specifications mean that an 8 Gb DDR5 DRAM chip can hit a considerably higher I/O speed than an 8 Gb commercial DDR4 IC today at a ~9% lower voltage. JEDEC plans that eventually the DDR5 interface will get to 6400 MT/s, but Cadence says that initial DDR5 memory ICs will support ~4400 MT/s data rates. This will be akin to DDR4 rising from DDR4-2133 at initial launch to DDR4-3200 today. Cadence's DDR5 demo video can be watched [youtube.com] here.

[...] There is a great demand for high DRAM capacity from various applications these days, but modern servers can physically accommodate a limited number of memory modules, and contemporary memory controllers can handle a limited number of DIMMs per channel. Therefore, to increase per-machine capacity of DRAM, manufacturers of memory need to build chips of higher capacity. The DDR5 standard enables memory makers to produce 16 Gb and 32 Gb chips by adding internal ECC to boost yields, although memory subsystems will still have to support their own ECC. The new standard also allows for optimizing internal segmentation and optimized timings. In addition to boosting maximum per-die capacity to 32 Gb (we are probably not going to see such DDR5 devices any time soon), JEDEC wants to make vertical stacking easier to simplify building chips based on multi-die chips. In fact, Marc Greenberg, director of DRAM IP marketing at Cadence, goes as far as saying that: "DDR5 is mostly a capacity solution, more than performance."

Related: DDR5 Standard to be Finalized by JEDEC in 2018 [soylentnews.org]
Samsung Announces Mass Production of GDDR6 SDRAM [soylentnews.org]

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