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posted by mrpg on Sunday May 06 2018, @04:07PM   Printer-friendly
from the 111100001 dept.

Cadence and Micron Demo DDR5-4400 IMC and Memory, Due in 2019

Cadence this week introduced the industry's first IP interface in silicon for the current provisional DDR5 specification developed by JEDEC. Cadence's IP and test chip [are] fabricated using TSMC's 7 nm process technology, and is designed to enable SoC developers to begin on their DDR5 memory subsystems now and get them to market in 2019-2020, depending on high-volume DDR5 availability. At a special event, Cadence teamed up with Micron to demonstrate their DDR5 DRAM subsystem. In the meantime, Micron has started to sample its preliminary DDR5 chips to interested parties.

Cadence's DDR5 memory controller and PHY achieve a 4400 MT/s data rate with CL42 using Micron's prototype 8 Gb DDR5 memory chips. Compared to DDR4 today, the supply voltage of DDR5 is dropped from 1.2 volts to 1.1 volts, with an allowable fluctuation range of only ±0.033 V. In this case, the specifications mean that an 8 Gb DDR5 DRAM chip can hit a considerably higher I/O speed than an 8 Gb commercial DDR4 IC today at a ~9% lower voltage. JEDEC plans that eventually the DDR5 interface will get to 6400 MT/s, but Cadence says that initial DDR5 memory ICs will support ~4400 MT/s data rates. This will be akin to DDR4 rising from DDR4-2133 at initial launch to DDR4-3200 today. Cadence's DDR5 demo video can be watched here.

There is a great demand for high DRAM capacity from various applications these days, but modern servers can physically accommodate a limited number of memory modules, and contemporary memory controllers can handle a limited number of DIMMs per channel. Therefore, to increase per-machine capacity of DRAM, manufacturers of memory need to build chips of higher capacity. The DDR5 standard enables memory makers to produce 16 Gb and 32 Gb chips by adding internal ECC to boost yields, although memory subsystems will still have to support their own ECC. The new standard also allows for optimizing internal segmentation and optimized timings. In addition to boosting maximum per-die capacity to 32 Gb (we are probably not going to see such DDR5 devices any time soon), JEDEC wants to make vertical stacking easier to simplify building chips based on multi-die chips. In fact, Marc Greenberg, director of DRAM IP marketing at Cadence, goes as far as saying that: "DDR5 is mostly a capacity solution, more than performance."

Related: DDR5 Standard to be Finalized by JEDEC in 2018
Samsung Announces Mass Production of GDDR6 SDRAM

Original Submission

Related Stories

DDR5 Standard to be Finalized by JEDEC in 2018 13 comments

JEDEC has announced that it expects to finalize the DDR5 standard by next year. It says that DDR5 will double bandwidth and density, and increase power efficiency, presumably by lowering the operating voltages again (perhaps to 1.1 V). Availability of DDR5 modules is expected by 2020:

You may have just upgraded your computer to use DDR4 recently or you may still be using DDR3, but in either case, nothing stays new forever. JEDEC, the organization in charge of defining new standards for computer memory, says that it will be demoing the next-generation DDR5 standard in June of this year and finalizing the standard sometime in 2018. DDR5 promises double the memory bandwidth and density of DDR4, and JEDEC says it will also be more power-efficient, though the organization didn't release any specific numbers or targets.

The DDR4 SDRAM specification was finalized in 2012, and DDR3 in 2007, so DDR5's arrival is to be expected (cue the Soylentils still using DDR2). One way to double the memory bandwidth of DDR5 is to double the DRAM prefetch to 16n, matching GDDR5X.

Graphics cards are beginning to ship with GDDR5X. Some graphics cards and Knights Landing Xeon Phi chips include High Bandwidth Memory (HBM). A third generation of HBM will offer increased memory bandwidth, density, and more than 8 dies in a stack. Samsung has also talked about a cheaper version of HBM for consumers with a lower total bandwidth. SPARC64 XIfx chips include Hybrid Memory Cube. GDDR6 SDRAM could raise per-pin bandwidth to 14 Gbps, from the 10-14 Gbps of GDDR5X, while lowering power consumption.

Original Submission

Samsung Announces Mass Production of GDDR6 SDRAM 16 comments

Samsung has announced the mass production of 16 Gb GDDR6 SDRAM chips with a higher-than-expected pin speed. The chips could see use in upcoming graphics cards that are not equipped with High Bandwidth Memory:

Samsung has beaten SK Hynix and Micron to be the first to mass produce GDDR6 memory chips. Samsung's 16Gb (2GB) chips are fabricated on a 10nm process and run at 1.35V. The new chips have a whopping 18Gb/s pin speed and will be able to reach a transfer rate of 72GB/s. Samsung's current 8Gb (1GB) GDDR5 memory chips, besides having half the density, work at 1.55V with up to 9Gb/s pin speeds. In a pre-CES 2018 press release, Samsung briefly mentioned the impending release of these chips. However, the speed on release is significantly faster than the earlier stated 16Gb/s pin speed and 64GB/s transfer rate.

18 Gbps exceeds what the JEDEC standard calls for.

Also at Engadget and Wccftech.

Related: GDDR5X Standard Finalized by JEDEC
DDR5 Standard to be Finalized by JEDEC in 2018
SK Hynix to Begin Shipping GDDR6 Memory in Early 2018
Samsung's Second Generation 10nm-Class DRAM in Production

Original Submission

Cadence and Micron Plan Production of 16 Gb DDR5 Chips in 2019 8 comments

Cadence & Micron DDR5 Update: 16 Gb Chips on Track for 2019

Earlier this year Cadence and Micron performed the industry's first public demonstration of next-generation DDR5 memory. At a TSMC event earlier this month the two companies provided some updates concerning development of the new memory technology. As it appears, the spec has not been finalized at JEDEC yet, but Micron still expects to start production of DDR5 memory chips in late 2019.

As noted back in May, the primary feature of DDR5 SDRAM is capacity of chips, not just a higher performance and a lower power consumption. DDR5 is expected to bring in I/O speeds of 4266 to 6400 MT/s, with a supply voltage drop to 1.1 V and an allowable fluctuation range of 3% (i.e., at ±0.033V). It is also expected to use two independent 32/40-bit channels per module (without/or with ECC). Furthermore, DDR5 will have an improved command bus efficiency (because the channels will have their own 7-bit Address (Add)/Command (Cmd) buses), better refresh schemes, and an increased bank group for additional performance. In fact, Cadence goes as far as saying that improved functionality of DDR5 will enable a 36% higher real-world bandwidth when compared to DDR4 even at 3200 MT/s (this claim will have to be put to a test) and once 4800 MT/s speed kicks in, the actual bandwidth will be 87% higher when compared to DDR4-3200. In the meantime, one of the most important features of DDR5 will be monolithic chip density beyond 16 Gb.

Leading DRAM makers already have monolithic DDR4 chips featuring a 16 Gb capacity, but those devices cannot offer extreme clocks or I/O speeds because of laws of physics. Therefore, companies like Micron have a lot of work to do in a bid to bring together high DRAM densities and performance in the DDR5 era. In particular, Micron is concerned about variable retention time, and other atomic level occurrences, once production technologies used for DRAM reach 10 – 12 nm. Meanwhile, the DDR5 Add/Cmd bus already features on-die termination to make signals cleaner and to improve stability at high data rates. Furthermore, high-end DDR5 DIMMs will have their own voltage regulators and PMICs. Long story short, while the DDR5 standard is tailored to wed performance and densities, there is still a lot of magic to be done by DRAM manufacturers.

Previously: DDR5 Standard to be Finalized by JEDEC in 2018
DDR5-4400 Test Chip Demonstrated

Original Submission

JEDEC Releases DDR5 Memory Specification 11 comments

DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond

We'll start with a brief look at capacity and density, as this is the most-straightforward change to the standard compared to DDR4. Designed to span several years (if not longer), DDR5 will allow for individual memory chips up to 64Gbit in density, which is 4x higher than DDR4's 16Gbit density maximum. Combined with die stacking, which allows for up to 8 dies to be stacked as a single chip, then a 40 element LRDIMM can reach an effective memory capacity of 2TB. Or for the more humble unbuffered DIMM, this would mean we'll eventually see DIMM capacities reach 128GB for your typical dual rank configuration.

[...] For DDR5, JEDEC is looking to start things off much more aggressively than usual for a DDR memory specification. Typically a new standard picks up from where the last one started off, such as with the DDR3 to DDR4 transition, where DDR3 officially stopped at 1.6Gbps and DDR4 started from there. However for DDR5 JEDEC is aiming much higher, with the group expecting to launch at 4.8Gbps, some 50% faster than the official 3.2Gbps max speed of DDR4. And in the years afterwards, the current version of the specification allows for data rates up to 6.4Gbps, doubling the official peak of DDR4.

Of course, sly enthusiasts will note that DDR4 already goes above the official maximum of 3.2Gbps (sometimes well above), and it's likely that DDR5 will eventually go a similar route. The underlying goal, regardless of specific figures, is to double the amount of bandwidth available today from a single DIMM. So don't be too surprised if SK Hynix indeed hits their goal of DDR5-8400 later this decade.

[...] JEDEC is also using the introduction of the DDR5 memory standard to make a fairly important change to how voltage regulation works for DIMMs. In short, voltage regulation is being moved from the motherboard to the individual DIMM, leaving DIMMs responsible for their own voltage regulation needs. This means that DIMMs will now include an integrated voltage regulator, and this goes for everything from UDIMMs to LRDIMMs.

JEDEC is dubbing this "pay as you go" voltage regulation, and is aiming to improve/simplify a few different aspects of DDR5 with it. The most significant change is that by moving voltage regulation on to the DIMMs themselves, voltage regulation is no longer the responsibility of the motherboard. Motherboards in turn will no longer need to be built for the worst-case scenario – such as driving 16 massive LRDIMMs – simplifying motherboard design and reining in costs to a degree. Of course, the flip side of this argument is that it moves those costs over to the DIMM itself, but then system builders are at least only having to buy as much voltage regulation hardware as they have DIMMs, and hence the PAYGO philosophy.

"On-die ECC" is mentioned in the press release and slides. If you can figure out what that means, let us know.

See also: Micron Drives DDR5 Memory Adoption with Technology Enablement Program

Previously: DDR5 Standard to be Finalized by JEDEC in 2018
DDR5-4400 Test Chip Demonstrated
Cadence and Micron Plan Production of 16 Gb DDR5 Chips in 2019
SK Hynix Announces Plans for DDR5-8400 Memory, and More

Original Submission

SK Hynix Ready to Ship 16 Gb DDR5 Dies, Has Its Own 64 GB DDR5-4800 Modules 7 comments

DDR5 is Coming: First 64GB DDR5-4800 Modules from SK Hynix

DDR5 is the next stage of platform memory for use in the majority of major compute platforms. The specification (as released in July 2020) brings the main voltage down from 1.2 V to 1.1 V, increases the maximum silicon die density by a factor 4, doubles the maximum data rate, doubles the burst length, and doubles the number of bank groups. Simply put, the JEDEC DDR specifications allows for a 128 GB unbuffered module running at DDR5-6400. RDIMMs and LRDIMMs should be able to go much higher, power permitting.

[...] SK Hynix's announcement today is that they are ready to start shipping DDR5 ECC memory to module manufacturers – specifically 16 gigabit dies built on its 1Ynm process that support DDR5-4800 to DDR5-5600 at 1.1 volts. With the right packaging technology (such as 3D TSV), SK Hynix says that partners can build 256 GB LRDIMMs. Additional binning of the chips for better-than-JEDEC speeds will have to be done by the module manufacturers themselves. SK Hynix also appears to have its own modules, specifically 32GB and 64GB RDIMMs at DDR5-4800, and has previously promised to offer memory up to DDR5-8400.

[...] As part of the announcement, it was interesting to see Intel as one of the lead partners for these modules. Intel has committed to enabling DDR5 on its Sapphire Rapids Xeon processor platform, due for initial launch in late 2021/2022. AMD was not mentioned with the announcement, and neither were any Arm partners.

SK Hynix quotes that DDR5 is expected to be 10% of the global market in 2021, increasing to 43% in 2024. The intersection point for consumer platforms is somewhat blurred at this point, as we're probably only half-way through (or less than half) of the DDR4 cycle. Traditionally we expect a cost interception between old and new technology when they are equal in market share, however the additional costs in voltage regulation that DDR5 requires is likely to drive up module costs – scaling from standard power delivery on JEDEC modules up to a beefier solution on the overclocked modules. It should however make motherboards cheaper in that regard.

See also: Insights into DDR5 Sub-timings and Latencies

Previously: DDR5 Standard to be Finalized by JEDEC in 2018
DDR5-4400 Test Chip Demonstrated
Cadence and Micron Plan Production of 16 Gb DDR5 Chips in 2019
SK Hynix Announces Plans for DDR5-8400 Memory, and More
JEDEC Releases DDR5 Memory Specification

Original Submission

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  • (Score: 1, Interesting) by Anonymous Coward on Sunday May 06 2018, @05:10PM

    by Anonymous Coward on Sunday May 06 2018, @05:10PM (#676403)

    4400 MT/s data rate

    4400 Mega Transfers per Second is 2200 MHz x2 for DDR.

  • (Score: 3, Interesting) by Rosco P. Coltrane on Sunday May 06 2018, @05:27PM (3 children)

    by Rosco P. Coltrane (4757) on Sunday May 06 2018, @05:27PM (#676408)

    Keep long-haired cats away from the PC - especially if they've been rubbing themselves on the carpet.

    • (Score: 3, Interesting) by takyon on Sunday May 06 2018, @05:49PM (2 children)

      by takyon (881) <> on Sunday May 06 2018, @05:49PM (#676412) Journal

      Fear the coronal mass ejection.

      [SIG] 10/28/2017: Soylent Upgrade v14 []
      • (Score: 2) by Rosco P. Coltrane on Sunday May 06 2018, @07:36PM (1 child)

        by Rosco P. Coltrane (4757) on Sunday May 06 2018, @07:36PM (#676429)

        Is that when a charged cat sheds its hair? :)

        • (Score: 2) by c0lo on Monday May 07 2018, @02:03AM

          by c0lo (156) Subscriber Badge on Monday May 07 2018, @02:03AM (#676534) Journal

          Keep long-haired cats away from the PC

          Fear the coronal mass ejection.

          Is that when a charged cat sheds its hair? :)

          Yes. Well... almost.
          The only minor thing that is needed additionally is that the cat must have enough mass to compress its guts to level fusion reaction is sustainable.


  • (Score: 2) by shortscreen on Sunday May 06 2018, @09:32PM (2 children)

    by shortscreen (2252) on Sunday May 06 2018, @09:32PM (#676448) Journal

    Why are high data rates for system memory only coming along now after GDDR5 has been around for ~9 years already?

    Also, DDR5-4400 CL42 doesn't sound like very good latency compared to DDR-400 CL3.

    • (Score: 0) by Anonymous Coward on Sunday May 06 2018, @11:16PM

      by Anonymous Coward on Sunday May 06 2018, @11:16PM (#676471)

      That latency value is measured in clock cycles. So you can't compare that number without the frequency as well. Admittedly, even then, it's a couple of nanoseconds slower on the ddr4. But it more than makes up for that in the crazy improvement in bandwidth.

    • (Score: 2) by bob_super on Monday May 07 2018, @04:57PM

      by bob_super (1357) on Monday May 07 2018, @04:57PM (#676687)

      Single-ended signalling doesn't like high-speed.
      It took them a very long time to come up with the standard, because reliable 4400MT/s per pin through a connector and quite a few inches of cheap PCB at low voltage using as little total power as possible ... is really f___ing hard.
      GDDR is simpler, starting with shorter reach and soldered chips. Isn't 4400 much faster than current GDDR ?

      I was talking to a customer a few years ago, when the DDR5 standard wasn't final, about the multi-level multi-pin arrangement they were considering to always have opposite transitions and max margin, combining the values of multiple wires to derive multiple bits in the process. I didn't read the final standard, but I sure hope they ended up with something simpler and less insane to validate and debug.

  • (Score: 3, Informative) by MichaelDavidCrawford on Sunday May 06 2018, @10:50PM (4 children)

    My Linux box never swaps

    Yes I Have No Bananas. []
    • (Score: 0) by Anonymous Coward on Monday May 07 2018, @12:42AM (3 children)

      by Anonymous Coward on Monday May 07 2018, @12:42AM (#676502)

      Run Firefox and watch free RAM be rapidly consumed... (Win version).
      For some reason, opening pdfs in a FF tab seems to make it really unstable(??)

  • (Score: 0) by Anonymous Coward on Monday May 07 2018, @03:31AM (1 child)

    by Anonymous Coward on Monday May 07 2018, @03:31AM (#676545)

    Does jedec spec specifies cooling? I miss the days when PCs didn't need no loud fans along with all the dust clogup killing the machines.

  • (Score: 0) by Anonymous Coward on Wednesday May 09 2018, @07:01PM

    by Anonymous Coward on Wednesday May 09 2018, @07:01PM (#677567)

    A: DDR memory