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takyon [soylentnews.org] writes:

JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard [jedec.org]

JEDEC Solid State Technology Association [jedec.org], the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard.

[...] JEDEC standard JESD235B for HBM leverages Wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB – 24 GB per stack.

This update extends the per pin bandwidth to 2.4 Gbps, adds a new footprint option to accommodate the 16 Gb-layer and 12-high configurations for higher density components, and updates the MISR polynomial options for these new configurations.

Some existing High Bandwidth Memory [wikipedia.org] products already had a per pin bandwidth of 2.4 Gbps. However, the increase in stack size and density could allow a product with 96 GB of DRAM using just four stacks (16 Gb DRAM × 12 × 4), up from 32 GB (8 Gb DRAM × 8 × 4).

This update apparently applies to HBM2 and is not considered a [arstechnica.com] third [notebookcheck.net] or fourth generation of HBM.

Also at Wccftech [wccftech.com].

Previously: Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks [soylentnews.org]

Original Submission