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posted by martyb on Sunday June 04 2017, @12:33PM   Printer-friendly
from the tiny-advances dept.

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.

Source.

But how many transistors per square millimeter is it?


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  • (Score: 0) by Anonymous Coward on Sunday June 04 2017, @11:07PM

    by Anonymous Coward on Sunday June 04 2017, @11:07PM (#520425)

    So, will the power saving from smaller chip features exceed the extreme amount of power used by EUV during manufacture? I don't know enough to do the envelope calculation, anyone have a clue? 2MW is a lot of power, and a wafer goes through weeks of process steps.

    Car analogy -- Like payback on a Prius, eventually the extra first cost is recouped in fuel savings, as long as you drive enough miles and the price of gasoline is high enough.