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posted by martyb on Sunday June 04 2017, @12:33PM   Printer-friendly
from the tiny-advances dept.

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.


But how many transistors per square millimeter is it?

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  • (Score: 2) by martyb on Monday June 05 2017, @07:08AM (1 child)

    by martyb (76) on Monday June 05 2017, @07:08AM (#520606) Journal

    > break the barriers of Moore’s law scaling

    Moore's law, when used as a predictive statement, indicates that the number of transistors that will fit on a die will grow exponentially. It has therefore been used to predict that there will be *no barriers*. (Not that it was intended to be a long-term predictive statement, and the teenies and twenties can definitely be considered the distant future of when it was made.)

    Close, but not quite. This is a commonly-repeated but misunderstood aspect of Moore's Law. It was not just about exponential growth. Gordon Moore made a prediction regarding the number of transistors that could be produced at minimum cost.

    Refer to "PROCEEDINGS OF THE IEEE, VOL. 86, NO. 1, JANUARY 1998 [] (pdf)" which, in turn, stated: "Reprinted from Gordon E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, pp. 114­117, April 19, 1965. Publisher Item Identifier S 0018-9219(98)00753-1."

    An excerpt follows, with my emphasis added:


    Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. For simple circuits, the cost per component is nearly inversely proportional to the number of components, the result of the equivalent piece of semiconductor in the equivalent package containing more components. But as components are added, decreased yields more than compensate for the increased complexity, tending to raise the cost per component. Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph). If we look ahead five years, a plot of costs suggests that the minimum cost per component might be expected in circuits with about 1000 components per circuit (providing such circuit functions can be produced in moderate quantities). In 1970, the manufacturing cost per component can be expected to be only a tenth of the present cost.

    The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least ten years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65 000.

    The graph herein referenced is presented as "Figure 3" and includes the famous mapping of "Log2 of the number of components per integrated function" (y-axis) versus "date" (x-axis) and which depicts the oft-repeated "doubling of transistors per year". Having already stated in the text his qualification that these would be produced at minimum cost, and given that the text label on the y-axis already encompassed three physical lines in the graph, it is understandable that he did not also include the qualification "at minimum cost" in that label. It seems to me that some people glanced at the plot, saw the pattern, and neglected to read the text. They widely proclaimed their viewpoint (neglecting minimum cost) and eventually that is what people remember, instead of what Gordon Moore actually stated.

    The amazing thing, from my perspective, was that "law" was postulated in 1965 which is over FIFTY YEARS AGO! There were no cell phones, laptops, or even personal computers back then. We're talking computers that were minimally the size of refrigerators. Now think of the rate of change in electronics we've witnessed since then. That his "law" (more correctly "observation" -- but that takes too many syllables) has held true for such a long period of time utterly amazes me. Moore made an extrapolation based on a few years' worth of results, when we were basically just getting started with integrated circuits, and it has basically held true for decades!

    Now, back to THIS story, my take is based on two things. For better or worse, Samsung is based out of South Korea. I took this phrasing as simply being as an error of translation of an abstract concept. I understood it to mean: "we were approaching roadblocks which blocked our constructing smaller and smaller features.

    Visible light has a wavelength on the order of 500nm. Through tremendous feats of engineering, we've witnessed smaller and smaller features continue to roll out. As we step away from visible light into ultra-violet, it is possible to construct finer and finer features. But there are limits with what can be done. Creating those precise frequencies at sufficient power levels to use in photo-lithography was starting to look like a hard barrier. Many were pursuing different approaches that worked in theory, but putting that into practice continued to run into roadblocks. Maybe we HAD reached the end of Moore's Law?

    This press release is simply stating that they have found a way to overcome that limitation, that they have a means of using extreme ultra-violet, and that they plan to use that to develop "7nm" feature sizes. (I'll not get into the whole discussion as to what is actually measured when one speaks about, say a 10nm process step or feature size.)

    So, I'll grant you that it is not the clearest phrasing, but a little tolerance of a mis-translation to English explains it well enough for me.

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  • (Score: 2) by FatPhil on Monday June 05 2017, @10:37AM

    > I'll grant you that it is not the clearest phrasing, but a little tolerance of a mis-translation to English...

    Because Samsung are a small cash-strapped company who can't afford a proof-reader who is familiar with technology, yeah, right.
    I shouldn't be surprised, even the contract I signed with SR-UK (Samsung Research UK) was in pretty mangled English.

    Even Moore's English is a bit mangled, I'm sure he's talking about minimum cost per unit of functionality, which isn't the absolute minimum cost. MCUs are typically built on what might be considered very legacy processes (I guess 60-90, but I'm a bit out of touch), but they're not designed to have much functionality at all. Smaller than the smallest package size simply isn't worth it.
    Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves