Samsung has developed the first 12-layer High Bandwidth Memory stacks:
Samsung's 12-layer DRAM KGSDs (known good stack die) will feature 60,000 [through silicon via (TSV)] holes which is why the manufacturer considers its technology one of the most challenging packaging for mass production. Despite increase of the number of layers from eight to 12, thickness of the package will remain at 720 microns, so Samsung's partners will not have to change anything on their side to use the new technology. It does mean that we're seeing DRAM layers getting thinner, with acceptable yields for high-end products.
One of the first products to use Samsung's 12-layer DRAM packaging technology will be the company's 24 GB HBM2 KGSDs that will be mass produced shortly. These devices will allow developers of CPUs, GPUs, and FPGAs to install 48 GB or 96 GB of memory in case of 2048 or 4096-bit buses, respectively. It also allows for 12 GB and 6 GB stacks with less dense configurations.
"12-Hi" stacks were added to the HBM2 standard back in December, but there were no immediate plans by Samsung or SK Hynix to manufacture it.
Future AMD CPUs (particularly Epyc) may feature HBM stacks somewhere on the CPU die. Intel has already used its embedded multi-die interconnect bridge (EMIB) technology with HBM to create an advanced APU with AMD's own graphics, and is using HBM on field programmable gate arrays (FPGAs) and other products.
AMD's Radeon VII GPU has 16 GB of HBM2. Nvidia's V100 GPU has 16 or 32 GB on a 4,096-bit memory bus.
Also at Electronics Weekly.
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An Intel website leaked some details of the Intel Core i7-8809G, a "Kaby Lake" desktop CPU with on-package AMD Radeon graphics and High Bandwidth Memory 2.0. While it is listed as an 8th-generation part, 8th-generation "Coffee Lake" CPUs for desktop users have up to 6 cores (in other words, Intel has been releasing multiple microarchitectures as "8th-generation"). The i7-8809G may be officially announced at the Consumer Electronics Show next week.
The components are linked together using what Intel calls "embedded multi-die interconnect bridge technology" (EMIB). The thermal design power (TDP) of the entire package is around 100 Watts:
Intel at the original launch did state that they were using Core-H grade CPUs for the Intel with Radeon Graphics products, which would mean that the CPU portion is around 45W. This would lead to ~55W left for graphics, which would be in the RX 550 level: 8 CUs, 512 SPs, running at 1100 MHz. It is worth nothing that AMD already puts up to 10 Vega CUs in its 15W processors, so with the Intel i7-8809G product Intel has likely has gone wider and slower: judging by the size of the silicon in the mockup, this could be more of a 20-24 CU design built within that 55W-75W window, depending on how the power budget is moved around between CPU and GPU. We await more information, of course.
It is rumored to include 4 GB of HBM2 on-package, while the CPU also supports DDR4-2400 memory. Two cheaper EMIB CPUs have been mentioned:
According to some other media, the 8809G will turbo to 4.1 GHz, while the graphics will feature 24 [compute units (CUs)] (1536 [stream processors (SPs)]) running at 1190 MHz while the HBM2 is 4GB and will run at 800 MHz. The same media are also listing the Core i7-8705G (20 CUs, 1000 MHz on 'Vega M GL', 700 MHz on HBM2) and a Core i7-8706G. None of the information from those sources is yet to be verified by AnandTech or found on an official Intel webpage.
Currently available AMD Ryzen Mobile APUs only include 8-10 Vega CUs. These are mobile chips with a maximum TDP of 25 W; no desktop Ryzen chips with integrated graphics have been announced yet.
Previously: Intel Announces Core H Laptop Chips With AMD Graphics and High Bandwidth Memory
JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard
JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard.
[...] JEDEC standard JESD235B for HBM leverages Wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB – 24 GB per stack.
This update extends the per pin bandwidth to 2.4 Gbps, adds a new footprint option to accommodate the 16 Gb-layer and 12-high configurations for higher density components, and updates the MISR polynomial options for these new configurations.
Some existing High Bandwidth Memory products already had a per pin bandwidth of 2.4 Gbps. However, the increase in stack size and density could allow a product with 96 GB of DRAM using just four stacks (16 Gb DRAM × 12 × 4), up from 32 GB (8 Gb DRAM × 8 × 4).
This update apparently applies to HBM2 and is not considered a third or fourth generation of HBM.
Also at Wccftech and AnandTech.
Previously: Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks
(Score: 0) by Anonymous Coward on Tuesday October 08 2019, @01:36PM (1 child)
I just looked at the spec.
They have multiple separate banks, each with a separate row and column control interface.
The controller can schedule refresh on each bank separately using a builtin row counter.
But if you accessed the row, it doesn't need to refresh, but the builtin counter makes it impossible to skip?
(Score: 0) by Anonymous Coward on Thursday October 10 2019, @11:16AM
I know some memory both requires a regular refresh charge, but also can become depleted during an access. If that is the case here it may be necessary even during an access to automatically refresh the accessed cells in order to avoid data corruption. Seems a little iffy, but everything below 28nm seems horribly iffy, and except for power consumption I have a lot more faith in 45nm as a minimum reliable feature size, and maybe much bigger if you want the hardware to last decades.
(Score: 3, Touché) by DannyB on Tuesday October 08 2019, @02:04PM (2 children)
First we had Azul's C4 garbage collector [azul.com] for heaps of hundreds of GB with pause times in the milliseconds.
Then we got both of Red Hat's Shenandoah [java.net], and Oracle's ZGC [java.net], for Terabytes of heap with 1 ms GC pause times. (call me when your python can do that!)
At this rate we're going to have enough memory to run the Java Hello World Enterprise Edition [github.com] any day now! And machines with 768 cores! Exciting stuff for us Java developers!
The lower I set my standards the more accomplishments I have.
(Score: 2) by DannyB on Tuesday October 08 2019, @02:06PM (1 child)
It may even become possible to compile and run the Java version of FizzBuzz Enterprise Edition [github.com].
FizzBuzz Enterprise Edition is a no-nonsense implementation of FizzBuzz made by serious businessmen for serious business purposes.
The lower I set my standards the more accomplishments I have.
(Score: 2) by Booga1 on Wednesday October 09 2019, @12:36AM
The bug reports on that are mildly entertaining.