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posted by Fnord666 on Wednesday December 11 2019, @08:09AM   Printer-friendly [Skip to comment(s)]
from the small-roads-on-that-map dept.

Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm

One of the interesting disclosures here at the IEEE International Electron Devices Meeting (IEDM) has been around new and upcoming process node technologies. Almost every session so far this week has covered 7nm, 5nm, and 3nm processes (as the industry calls them). What we didn't expect to see disclosed was an extended roadmap of Intel's upcoming manufacturing processes.

[...] Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then 5nm in 2023, 3nm in 2025, 2nm in 2027, and 1.4 nm in 2029. This is the first mention on 1.4nm for Intel on any slide, so this confirms where Intel is going, and just for context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.

It is perhaps worth noting that some of the talks at this year's IEDM features dimensions on the order of 0.3nm with what are called '2D self-assembly' materials, so something this low isn't unheard of, but it is unheard of in silicon. Obviously there are many issues going that small that Intel (and its partners) will have to overcome.

Inbetween each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. Intel believes they can do this on a yearly cadence, but also have overlapping teams to ensure that one full process node can overlap with another.

The interesting element to this slide is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older '++' version of a process node in the same timeframe. Despite Intel stating that they are disaggregating chip design from process node technology, at some point there has to be a commitment to a process node in order to start the layouts in silicon. At that point the process node procedure is kind of locked, especially when it goes to mask creation.


Original Submission

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Intel Says Process Tech to Lag Competitors Until Late 2021, Will Regain Lead with 5nm (archive)

It appears that 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday covering a wide range of topics, but noted that despite being "undoubtedly in the 10nm era," the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021. Davis also said that Intel wouldn't regain process leadership until it produces the 5nm node at an unspecified date.

Davis commented that the company was "definitely in the 10nm era" with Ice Lake client chips and networking ASICs already shipping, along with the pending release of discrete GPUs and Ice Lake Xeons. Intel is also moving well along the path of inter-node development, which consists of "+" revisions to existing processes. Davis said the 10nm inter-node step provides a "step-function move" with the Tiger Lake chips based on the 10nm+ process as the company awaits its 7nm process.

However, Davis noted that in spite of the shipping products and pending "+" revisions to the 10nm process, its process node still lags behind competitors, stating:

"So we bring a lot of capability to the table for our customers, in addition to the CPU, and we feel like we're starting to see the acceleration on the process side that we have been talking about to get back to parity in the 7nm generation and regain leadership in the 5nm generation."

Previously:
Intel Launches Coffee Lake Refresh, Roadmap Leaks Showing No "10nm" Desktop Parts Until 2022
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan
Intel Roadmap Shows Plans for "5nm", "3nm", "2nm", and "1.4nm" Process Nodes by 2029


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  • (Score: 0) by Anonymous Coward on Wednesday December 11 2019, @12:06PM (1 child)

    by Anonymous Coward on Wednesday December 11 2019, @12:06PM (#931019)

    I"m still waiting for them to ship Gemini Lake in quantity.

  • (Score: 0) by Anonymous Coward on Wednesday December 11 2019, @01:48PM (1 child)

    by Anonymous Coward on Wednesday December 11 2019, @01:48PM (#931035)

    Intel has shown zero ability to stick to their roadmaps since 2016, that's 4 years now!

    • (Score: 2) by takyon on Wednesday December 11 2019, @01:54PM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday December 11 2019, @01:54PM (#931037) Journal

      ASML, the sole provider of extreme ultraviolet lithography tools, was supposed to deliver them as early as 2007.

      With EUV, Intel actually has a chance of getting back on track. Although Intel's competitors will not be standing still.

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  • (Score: 0) by Anonymous Coward on Wednesday December 11 2019, @02:02PM (3 children)

    by Anonymous Coward on Wednesday December 11 2019, @02:02PM (#931039)

    Okay, so I'm assuming they are copper atoms (which isn't right). A copper atom is about 2.3*10^-10 (or 0.23 nm) in diameter. That's pretty insane.

    Reference: https://www.chegg.com/homework-help/questions-and-answers/diameter-copper-atom-approximately-228e-10-m-massof-one-mole-copper-64-grams-assume-atoms--q181830 [chegg.com]

    • (Score: 2) by takyon on Wednesday December 11 2019, @02:16PM (2 children)

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday December 11 2019, @02:16PM (#931042) Journal

      They are marketing names for far in the future nodes so who knows what it really means. But we can expect several density increases and efficiency benefits from Intel, TSMC, Samsung, or others.

      Everything could benefit, but smaller nodes could enable new form factors. We already have smartglasses and smartwatches, how about nanobots?

      I'm guessing AMD will eventually start adding integrated graphics to almost every chip like Intel does, because it can cost almost nothing in terms of die size on some of these smaller nodes.

      "90nm" 3DSoC [darpa.mil] is supposed to be far faster than "7nm" 2D chips. What about a "1.4nm" or "0.3nm" 3DSoC, if it's possible to make one? Or a different 3D design. Scaling all the way down and then layering up could allow neuromorphic designs to deliver human level AI in less than 1.5 liters.

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      • (Score: 2) by HiThere on Wednesday December 11 2019, @04:52PM (1 child)

        by HiThere (866) on Wednesday December 11 2019, @04:52PM (#931123) Journal

        Unfortunately, it's Intel, so we can expect the numbers to be manipulated or faked when they start selling them. And a whole **** of new exploits.

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        • (Score: 2) by takyon on Wednesday December 11 2019, @05:01PM

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday December 11 2019, @05:01PM (#931127) Journal

          I have no plans to buy Intel. If they pull something out of their hat and manage to leapfrog AMD in perf/$, I'll just wait a few months for AMD to make a comeback or cut prices.

          Then there's ARM (got 2x RasPi4B), RISC-V and otherz.

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  • (Score: 2) by FatPhil on Wednesday December 11 2019, @02:20PM (4 children)

    by FatPhil (863) <pc-soylentNO@SPAMasdf.fi> on Wednesday December 11 2019, @02:20PM (#931043) Homepage
    "if that 1.4nm is indicative of any actual feature"

    The "X nm" nomenclature hasn't corresponded to any feature for about a decade. There was an agreement that a 29% reduction in the linear scale denoting the technology wasn't convincing the punters that the density had doubled. (0.71*0.71 = 0.5), and therefore they should adopt an abstract quantity, with linear units, to denote a property which has squared units, so that doubling looked like doubling to punters who buy things purely because of abstract numbers printed on the side of the box rather than physical measurements of how well it solves the problem that needs solving (time and energy required).

    Here's a good summary of how things stand in reality, it's barely out of date as most things since, like this story, are slideware:
        https://www.techcenturion.com/7nm-10nm-14nm-fabrication
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    • (Score: 3, Interesting) by takyon on Wednesday December 11 2019, @02:40PM (3 children)

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday December 11 2019, @02:40PM (#931051) Journal

      If you do the math on the node numbers, you would expect density to double:

      142 / 102 = 1.96
      102 / 72 = 2.04081632653

      Intel's new CEO blamed the company [pcgamer.com] for pursuing a 2.7x transistor density increase on the "10nm" node, instead of 2x.

      Intel likes to tout transistors per mm2 [soylentnews.org] (when favorable).

      The node number doesn't give you other info, like potential performance or efficiency gains [anandtech.com].

      If "1.4nm" ends up being representative of anything and Intel can actually get it to work, then we'll see some unspecified but great transistor density increases. If not from Intel, then TSMC, Samsung, SMIC (China), or others can do it. "1.4nm" presumably is not a theoretical limit, since single-atom transistors are possible [wikipedia.org].

      After that, pray for femtocomputing [kurzweilai.net].

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      • (Score: 2) by FatPhil on Wednesday December 11 2019, @11:19PM (2 children)

        by FatPhil (863) <pc-soylentNO@SPAMasdf.fi> on Wednesday December 11 2019, @11:19PM (#931260) Homepage
        > If you do the math on the node numbers, you would expect density to double:

        You've completely missed my point, and the industry marketroids' point. In order to express "double density", they feel the need to use a half-sized linear number, so that people who *don't do the maths* will view it as a doubling. That's a consciously made, and publicly stated, decision. Doing the maths will only lead to confusion, don't do that. Someone should have told you this a decade ago, goodness knows how much marketting bullshit you've swallowed in that time.
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