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posted by cmn32480 on Tuesday April 05 2016, @06:06PM   Printer-friendly
from the everything-is-getting-smaller dept.

Samsung Electronics has announced the production of "10nm-class" 8 gigabit DRAM chips that will be used in DDR4 modules with capacities ranging from 4 GB to 128 GB. "10nm-class" is an industry term that refers to an unspecified process somewhere between 10 nanometers and 19 nanometers.

In November, Samsung announced the production of 128 GB DDR4 registered dual inline memory modules (RDIMMs) using through silicon via (TSV) stacked dies with four 8 gigabit chips per package. Those modules used 20nm process DRAM and achieved a 2,400 Mbps data rate. The new 10nm-class memory will support a 3,200 Mbps data rate.

Original Submission

Related Stories

Samsung Mass Produces 128 GB DDR4 Server Memory 12 comments

Samsung has developed the world's first 128 GB DDR4 registered memory modules for servers. From the press release:

Following Samsung's introduction of the world-first 3D TSV DDR4 DRAM (64GB) in 2014, the company's new TSV registered dual inline memory module (RDIMM) marks another breakthrough that opens the door for ultra-high capacity memory at the enterprise level. Samsung's new TSV DRAM module boasts the largest capacity and the highest energy efficiency of any DRAM modules today, while operating at high speed and demonstrating excellent reliability.

From The Register:

The Register is aware of servers with 96 DIMM slots, which means ... WOAH! ... 12.2 terabytes of RAM in a single server if you buy Samsung's new babies.

Samsung says these new DIMMS are special because "the chip dies are ground down to a few dozen micrometers, pierced with hundreds of fine holes and vertically connected by electrodes passing through the holes, allowing for a significant boost in signal transmission."

There's also "a special design through which the master chip of each 4GB package embeds the data buffer function to optimise module performance and power consumption."

Original Submission

Samsung Announces 8 GB DRAM Package for Mobile Devices 10 comments

Samsung has announced an 8 GB LPDDR4 DRAM package intended for smartphones and tablets, using four 16 Gb (2 GB) chips manufactured on a 10nm-class process (probably 18nm):

Samsung this week announced its first LPDDR4 memory chips made using its 10nm-class DRAM fabrication technology. The new DRAM ICs feature the industry's highest density of 16 Gb, are rated to run at 4266 MT/s data rate, and open the door to more mobile devices with 8 GB of DRAM.

Earlier this year Samsung started to produce DDR4 memory using its 10nm-class DRAM manufacturing process (which is believed to be 18 nm) and recently the firm began to use it to make LPDDR4 memory devices, just as it planned. The thinner fabrication technology allowed Samsung to increase capacity of a single LPDDR4 DRAM IC to 16 Gb (up from 12 Gb at 20nm introduced in August, 2015) while retaining a 4266 MT/s transfer rate.

The first product to use the 16 Gb ICs is Samsung's 8 GB LPDDR4-4266 mobile DRAM package for smartphones, tablets, and other applications that can use LPDDR4. The device stacks four memory ICs and provides up to 34 GB/s of bandwidth when connected to an SoC using a 64-bit memory bus. The 8 GB DRAM package comes in a standard 15 mm x 15 mm x 1 mm form-factor, which is compatible with typical mobile devices, but Samsung can also make the package thinner than 1 mm to enable PoP stacking with a mobile application processor or a UFS NAND storage device.

The press release confirms the high data rate:

The new 8GB LPDDR4 operates at up to 4,266 megabits per second (Mbps), which is twice as fast as DDR4 DRAM for PCs working typically at 2,133 Mbps per pin. Assuming a 64 bit (x64) wide memory bus, this can be viewed as transmitting over 34GBs of data per second.

Tune in next year when I post about Samsung putting 12 GB of RAM in smartphones.

Samsung Announces 12Gb LPDDR4 DRAM, Could Enable Smartphones With 6 GB of RAM
Samsung Announces "10nm-Class" 8 Gb DRAM Chips

Original Submission

Samsung's Second Generation 10nm-Class DRAM in Production 1 comment

Samsung's second generation ("1y-nm") 8 Gb DDR4 DRAM dies are being mass produced:

Samsung late on Wednesday said that it had initiated mass production of DDR4 memory chips using its second generation '10 nm-class' fabrication process. The new manufacturing technology shrinks die size of the new DRAM chips and improves their performance as well as energy efficiency. To do that, the process uses new circuit designs featuring air spacers (for the first time in DRAM industry). The new DRAM ICs (integrated circuits) can operate at 3600 Mbit/s per pin data rate (DDR4-3600) at standard DDR4 voltages and have been validated with major CPU manufacturers already.

[...] Samsung's new DDR4 chip produced using the company's 1y nm fabrication process has an 8-gigabit capacity and supports 3600 MT/s data transfer rate at 1.2 V. The new D-die DRAM runs 12.5% faster than its direct predecessor (known as Samsung C-die, rated for 3200 MT/s) and is claimed to be up to 15% more energy efficient as well. In addition, the latest 8Gb DDR4 ICs use a new in-cell data sensing system that offers a more accurate determination of the data stored in each cell and which helps to increase the level of integration (i.e., make cells smaller) and therefore shrink die size.

Samsung says that the new 8Gb DDR4 chips feature an "approximate 30% productivity gain" when compared to similar chips made using the 1x nm manufacturing tech.
UPDATE 12/21: Samsung clarified that productivity gain means increase in the number of chips per wafer. Since capacity of Samsung's C-die and D-die is the same, the increase in the number of dies equals the increase in the number of bits per wafer. Therefore, the key takeaway from the announcement is that the 1y nm technology and the new in-cell data sensing system enable Samsung to shrink die size and fit more DRAM dies on a single 300-mm wafer. Meanwhile, the overall 30% productivity gain results in lower per-die costs at the same yield and cycle time (this does not mean that the IC costs are 30% lower though) and increases DRAM bit output.

The in-cell data sensing system and air spacers will be used by Samsung in other upcoming types of DRAM, including DDR5, LPDDR5, High Bandwidth Memory 3.0, and GDDR6.

Also at Tom's Hardware.

Previously: Samsung Announces "10nm-Class" 8 Gb DRAM Chips

Related: Samsung Announces 12Gb LPDDR4 DRAM, Could Enable Smartphones With 6 GB of RAM
Samsung Announces 8 GB DRAM Package for Mobile Devices
Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks
IC Insights Predicts Additional 40% Increase in DRAM Prices

Original Submission

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  • (Score: 1, Interesting) by Anonymous Coward on Tuesday April 05 2016, @06:20PM

    by Anonymous Coward on Tuesday April 05 2016, @06:20PM (#327739)

    For the RAM:
    Is this new memory susceptible to rowhammer style attacks?
    Is it available in cost effective unregistered ECC modules?

    For the flash:
    How many write erase cycles is it good for?
    What is the MTBF?
    What is its power off data retention period? Still 10 years? Less?
    Are there any rowhamemr style leakage issues in the flash chips that could corrupt data?

    The smaller these processes get, the more concerned I am about the overall stability of the technology. It's not like these guys are trying for the best quality given the rapid turnover to be competitive on the time to market front.

    • (Score: 3, Informative) by takyon on Tuesday April 05 2016, @06:36PM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday April 05 2016, @06:36PM (#327743) Journal

      Here is a large version of the photo accompanying the press release: []

      Here are the specs of the 128 GB TSV 20nm DDR4, which is registered: []

      The website makes it fairly easy to search for other DRAM products.

      The press release mentions "4GB for notebook PCs to 128GB for enterprise servers".

      No NAND mentioned in this story.

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      • (Score: 2) by Alfred on Tuesday April 05 2016, @08:06PM

        by Alfred (4006) on Tuesday April 05 2016, @08:06PM (#327770) Journal
        Whoa, check that picture. The bottom edge with the contacts is not straight. I suppose this is to keep you from seating them in a DDR3 slot but really, couldn't they just make them a different size or another notch location? I'd prefer smaller size since I like building with ITX boards.

        And how many Bubba's IT Trailers will try and shave the PCB straight to use it somewhere they shouldn't ;-)
    • (Score: 3, Insightful) by bitstream on Tuesday April 05 2016, @09:23PM

      by bitstream (6144) on Tuesday April 05 2016, @09:23PM (#327790) Journal

      My thoughts too..
      Btw, why is unregistred RAM that important? extra buffers actually increase the electrical stability.

      The path to smaller and smaller geometry will end up where the uncertainty of matter will wreck the stability of the module. The superficially solid and stable surroundings is just an illusion. In reality all matter above 0 K is shaking and there's subatomic particles shoot out at near speed of light etc. These phenoma will matter a lot less of large geometries and small number of bits. ECC or RAM-RAID will become a necessity, just like harddiscs uses advanced trellis encoding to keep bits correct and ZFS software checks them again.

      Anyone placing these memory modules near a thick concrete wall, rocks or radon site will perhaps get a free geiger counter rather than RAM. Or the chassis and 19" rack is made of Chinese steel from scrapped nuclear sites.

      And don't forget the CAS latency (CL) that will make requesting data in a random rather than a sequential order really, really slow. Notice how the "old" DDR3 interface is actually better on this.

      Any comments?

  • (Score: 2) by Gravis on Tuesday April 05 2016, @07:06PM

    by Gravis (4596) on Tuesday April 05 2016, @07:06PM (#327755)

    the 14nm process [] is the only thing below 22nm that is in use. the actual 10nm process is still in development.

    • (Score: 4, Informative) by takyon on Tuesday April 05 2016, @07:22PM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday April 05 2016, @07:22PM (#327761) Journal

      Memory manufacturers use irregular processes, such as 15nm or 19nm mentioned in this story [], or 16nm-17nm here []. So no, it is not necessarily 14nm.

      For CPUs, there are other processes under 22nm... mainly 20nm and 16nm. 14nm is not the "only thing".

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      • (Score: 2) by bob_super on Tuesday April 05 2016, @09:08PM

        by bob_super (1357) on Tuesday April 05 2016, @09:08PM (#327785)

        and there is no real "14nm" dimension in that process either.
        Processes are named by marketing by dividing the old node by sqrt(2), but when you look at the exact feature sizes, it's a mixed bag, with some not even changing from one node to the next.

        • (Score: 2) by takyon on Tuesday April 05 2016, @09:49PM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday April 05 2016, @09:49PM (#327799) Journal

          Yeah, I read that article too (although I can't find it, was it IEEE?). The proof is in the pudding. Some feature sizes scale down, density and performance scale up, power consumption drops. We can be fairly certain that "10nm-class" DRAM will outperform "20nm" DRAM, and if it doesn't, benchmarks and other data will tell the tale.

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  • (Score: 0) by Anonymous Coward on Tuesday April 05 2016, @07:48PM

    by Anonymous Coward on Tuesday April 05 2016, @07:48PM (#327768)

    Or can I only read the press release?

    • (Score: 3, Informative) by takyon on Tuesday April 05 2016, @08:35PM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday April 05 2016, @08:35PM (#327773) Journal

      Mass production does not mean general availability.

      Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the ultra-HD smartphone market.

      While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.

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