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posted by Fnord666 on Tuesday January 08 2019, @10:02PM   Printer-friendly [Skip to comment(s)]
from the seeing-the-future dept.

CES 2019 Quick Bytes: Consumer 10nm is Coming with Intel's Ice Lake

We've been on Intel's case for years to tell us when its 10nm parts are coming to the mass market. Technically Intel already shipped its first 10nm processor, Cannon Lake, but this was low volume and limited to specific geographic markets. This time Intel is promising that its first volume consumer processor on 10nm will be Ice Lake. It should be noted that Intel hasn't put a date on Ice Lake launching, but has promised 10nm on shelves by the end of 2019. It has several products that could qualify for that, but Ice Lake is the likely suspect.

At Intel's Architecture Day in December, we saw chips designated as 'Ice Lake-U', built for 15W TDPs with four cores using the new Sunny Cove microarchitecture and Gen11 graphics. Intel went into some details about this part, which we can share with you today.

The 15W processor is a quad core part supporting two threads per core, and will have 64 EUs of Gen11 graphics. 64 EUs will be the standard 'GT2' mainstream configuration for this generation, up from 24 EUs today. In order to drive that many execution units, Intel stated that they need 50-60 GB/s of memory bandwidth, which will come from LPDDR4X memory. In order for those numbers to line up, they will need LPDDR4X-3200 at a minimum, which gives 51.2 GB/s. [...] For connectivity, the chips will support Wi-Fi 6 (802.11ax) if the laptop manufacturer uses the correct interface module, but the support for Wi-Fi 6 is in the chip. The processor also supports native Thunderbolt 3 over USB Type-C, marking the first Intel chip with native TB3 support.

CES 2019 Quick Bytes: Intel's 10nm Hybrid x86 Foveros Chip is Called Lakefield

The reason this chip exists is because one of Intel's customers requested a processor with integrated graphics that can idle at 2 milliwatts. After a few years of engineering, Intel is finally there. There's also another trick at play here.

The chip uses a combination of Intel's high power and low power cores. Inside the new chip, which Intel announced at CES is called Lakefield, is one of its high-powered Core architecture Sunny Cove cores, and four low-powered Tremont Atom cores. This is the first Intel chip, or consumer chip at least, to use both core designs at once. This is fairly common for Arm chips in smartphones, but we have not seen it yet in the PC space. We have a block diagram showing cache layouts and things, and at the first showing, Intel's Jim Keller said that the company were having fun with the technology with designing things that could become future parts.

Intel is also announcing an "AI" focused chip that will compete with Nvidia's similar GPU products:

Intel has just announced a brand new class of AI processor: the Intel Nervana NNP-1. This is one of the first truly powerful AI processors that Intel has promised to produce. All previous AI chips the company made were in the mWatt of power, this one is going to be in the "hundreds of watts" of power. While no specific details were given in the demo, it was inferred that the technology will take advantage of Intel's DL Boost technology to offer a CPU based competitor to GPUs.

See also: Intel's Keynote at CES 2019: 10nm, Ice Lake, Lakefield, Snow Ridge, Cascade Lake
Intel's New 9th Gen Desktop CPUs: i3-9350KF, i5-9400F, i5-9400, i5-9600KF, i7-9700KF, i9-9900KF


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Related Stories

Intel Not Focused on Defending High CPU Market Share 27 comments

Intel's CEO Bob Swan is looking beyond CPU market share:

"We think about having 30% share in a $230 billion [silicon] TAM[*] that we think is going to grow to $300 billion [silicon] TAM over the next 4 years, and frankly, I'm trying to destroy the thinking about having 90% share inside our company because, I think it limits our thinking, I think we miss technology transitions. we miss opportunities because we're, in some ways pre-occupied with protecting 90, instead of seeing a much bigger market with much more innovation going on, both Inside our four walls, and outside our four walls, so we come to work in the morning with a 30% share, with every expectation over the next several years, that we will play a larger and larger role in our customers success, and that doesn't just [mean] CPUs.

It means GPUs, it means Al, it does mean FPGAs, it means bringing these -technologies together so we're solving customers' problems. So, we're looking at a company with roughly 30% share in a $288 billion silicon TAM, not CPU TAM but silicon TAM. We look at the investments we've been making over the last several years in these kind of key technology inflections: 5G At autonomous, acquisitions, including Altera, that we think is more and more relevant both in the cloud but also ai the network and at the edge, and we see a much bigger opportunity, and our expectations are that we're going to gain our fair share at that much larger TAM by Investing in these key technology inflections." - Intel CEO Bob Swan

A 30% TAM in all of silicon would mean that Intel not only has more room to grow but is a lot more diversified as well. With the company working on the Nervana processor as well as its Xe GPU efforts, it seems poised to start clawing market share in new markets. Interestingly, it also means that Intel is not interested in defending its older title of being the CPU champion and will actually cede space to AMD where required. To me, this move is reminiscent of Lisa Su's decision to cede space in the GPU side of things to turn AMD around.

Intel's business strategy is now focused on whatever an "XPU" is as well as GPUs, FPGAs, machine learning accelerators, and next-generation memory/storage:

This means the company intends to continue making its heaviest bets in areas such as Optane storage, hardware Artificial Intelligence acceleration, 5G modems, data center networking, and more. The slide that really drives this commitment home comes from Q2's investor meeting that explicitly shows the company moving from a "protect and defend" strategy to a growth strategy. If this slide were in a sales meeting, it wouldn't say much—but delivered to the company's investors, it gains a bit of gravitas.

Most of this was revealed nearly six months ago at the company's May 2019 investor's meeting, but the Q3 investor's meeting last week continues with and strengthens this story for Intel's future growth, with slides more focused on Optane, network, and IoT/Edge market growth than with the traditional PC and server market.

[*] TAM = Total Addressable Market.

Related: Intel Promises "10nm" Chips by the End of 2019, and More
Intel's Interim CEO Robert Swan Becomes Full-Time CEO
AMD Gains Market Share in Desktops, Laptops, and Servers as of Q4 2018
PC Market Decline Blamed on Intel, AMD to See Gains
Intel Chip Shortages - at Least Another Quarter or Two to Go, Say PC Execs
Intel announces $20 billion increase in stock buybacks (from $4.5 billion)
Intel Xe High Performance Computing GPUs will use Chiplets


Original Submission

Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration 9 comments

Intel Lakefield SoC With Foveros 3D Packaging Previewed – 10nm Hybrid CPU Architecture Featuring Sunny Cove, Gen 11 Graphics and More

Intel Lakefield is based around Foveros technology which helps connect chips and chiplets in a single package that matches the functionality and performance of a monolithic SOC. Each die is then stacked using FTF micro-bumps on the active interposer through which TSVs are drilled to connect with solder bumps and eventually the final package. The whole SOC is just 12×12 (mm) which is 144mm2.

Talking about the SOC itself and its individual layers, the Lakefield SOC that has been previewed consists of at least four layers or dies, each serving a different purpose. The top two layers are composed of the DRAM which will supplement the processor as the main system memory. This is done through the PoP (Package on Package) memory layout which stacks two BGA DRAMs on top of each other as illustrated in the preview video. The SOC won't have to rely on socketed DRAM in this case which saves a lot of footprint on the main board.

The second layer is the Compute Chiplet with a Hybrid CPU architecture and graphics, based on the 10nm process node. The Hybrid CPU architecture has a total of five individual Cores, one of them is labeled as the Big Core which features the Sunny Cove architecture. That's the same CPU architecture that will be featured on Intel's upcoming 10nm Ice Lake processors. The Sunny Cove Core is optimized for high-performance throughput. There are also four small CPUs that are based on the 10nm process but optimized for power efficiency. The same die [has] Intel's Gen 11 graphics engine with 64 Execution Units.

[...] [Last] of all is the base die which serves as the cache and I/O block of the SOC. Labeled as the P1222 and based on a 22FFL process node, the base die comes with a low cost and low leakage design while providing a feature-rich array of I/O capabilities.

It would be nice to finally see some consumer CPUs with stacked DRAM, although the amount was not specified (8 GB?).

Intel video (1m48s). Also at Notebookcheck.

Previously: Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More


Original Submission

Leaked Intel Discrete Graphics Roadmap Reveals Plans for "Seamless" Dual, Quad, and Octa-GPUs 14 comments

Intel has teased* plans to return to the discrete graphics market in 2020. Now, some of those plans have leaked. Intel's Xe branded GPUs will apparently use an architecture capable of scaling to "any number" of GPUs that are connected by a multi-chip module (MCM). The "e" in Xe is meant to represent the number of GPU dies, with one of the first products being called X2/X2:

Developers won't need to worry about optimizing their code for multi-GPU, the OneAPI will take care of all that. This will also allow the company to beat the foundry's usual lithographic limit of dies that is currently in the range of ~800mm2. Why have one 800mm2 die when you can have two 600mm2 dies (the lower the size of the die, the higher the yield) or four 400mm2 ones? Armed with One API and the Xe macroarchitecture Intel plans to ramp all the way up to Octa GPUs by 2024. From this roadmap, it seems like the first Xe class of GPUs will be X2.

The tentative timeline for the first X2 class of GPUs was also revealed: June 31st, 2020. This will be followed by the X4 class sometime in 2021. It looks like Intel plans to add two more cores [dies] every year so we should have the X8 class by 2024. Assuming Intel has the scaling solution down pat, it should actually be very easy to scale these up. The only concern here would be the packaging yield – which Intel should be more than capable of handling and binning should take care of any wastage issues quite easily. Neither NVIDIA nor AMD have yet gone down the MCM path and if Intel can truly deliver on this design then the sky's the limit.

AMD has made extensive use of MCMs in its Zen CPUs, but will reportedly not use an MCM-based design for its upcoming Navi GPUs. Nvidia has published research into MCM GPUs but has yet to introduce products using such a design.

Intel will use an MCM for its upcoming 48-core "Cascade Lake" Xeon CPUs. They are also planning on using "chiplets" in other CPUs and mixing big and small CPU cores and/or cores made on different process nodes.

*Previously: Intel Planning a Return to the Discrete GPU Market, Nvidia CEO Responds
Intel Discrete GPU Planned to be Released in 2020
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More

Related: Intel Integrates LTE Modem Into Custom Multi-Chip Module for New HP Laptop
Intel Promises "10nm" Chips by the End of 2019, and More


Original Submission

Intel CEO Blames "10nm" Delays on Aggressive Density Target, Promises "7nm" for 2021 10 comments

Intel says it was too aggressive pursuing 10nm, will have 7nm chips in 2021

[Intel's CEO Bob] Swan made a public appearance at Fortune's Brainstorm Tech conference in Aspen, Colorado, on Tuesday and explained to the audience in attendance that Intel essentially set the bar too high for itself in pursuing 10nm. More specifically, he pointed to Intel's overly "aggressive goal" of going after a 2.7x transistor density improvement over 14nm.

[...] Needless to say, the 10nm delays have caused Intel to fall well behind that transistor density doubling. Many have proclaimed Moore's Law as dead, but as far as Swan is concerned, Moore's Law is not dead. It apparently just needed to undergo an unexpected surgery.

"The challenges of being late on this latest [10nm] node of Moore's Law was somewhat a function of what we've been able to do in the past, which in essence was define the odds on scaling the infrastructure," Swan explains. Bumping up to a 2.7x scaling factor proved to be "very complicated," more so than Intel anticipated. He also says that Intel erred when it "prioritized performance at a time when predictability was really important."

"The short story is we learned from it, we'll get our 10nm node out this year. Our 7nm node will be out in two years and it will be a 2.0X scaling so back to the historical Moore's Law curve," Swan added.

Also at Fortune and Tom's Hardware.

Related:


Original Submission

Intel Reveals Three New Packaging Technologies for Stitching Multiple Dies Into One Processor 12 comments

Intel will be using a few packaging technologies to connect CPU core "chiplets":

Intel revealed three new packaging technologies at SEMICON West: Co-EMIB, Omni-Directional Interconnect (ODI) and Multi-Die I/O (MDIO). These new technologies enable massive designs by stitching together multiple dies into one processor. Building upon Intel's 2.5D EMIB and 3D Foveros tech, the technologies aim to bring near-monolithic power and performance to heterogeneous packages. For the data-center, that could enable a platform scope that far exceeds the die-size limits of single dies.

[...] Compared to interposers, which can be reticle-sized (832mm2) or even larger, [EMIB (Embedded Multi-die Interconnect Bridge)] is just a small (hence, cheap) piece of silicon. It provides the same bandwidth and energy-per-bit advantages of an interposer compared to standard package traces, which are traditionally used for multi-chip packages (MCPs), such as AMD's Infinity Fabric. (To some extent, because the PCH is a separate die, chiplets have actually been around for a very long time.)

[...] Intel showed off a concept product that contains four Foveros stacks, with each stack having eight small compute chiplets that are connected via TSVs to the base die. (So the role of Foveros there is to connect the chiplets as if it were a monolithic die.) Each Foveros stack is then interconnected via two (Co-)EMIB links with its two adjacent Foveros stacks. Co-EMIB is further used to connect the HBM and transceivers to the compute stacks.

Evidently, the cost of such a product would be enormous, as it essentially contains multiple traditional monolithic-class products in a single package. That's likely why Intel categorized it as a data-centric concept product, aimed mainly at the cloud players that are more than happy to absorb those costs in exchange for the extra performance.

[...] When they are ready, these technologies will provide Intel with powerful capabilities for the heterogeneous and data-centric era. On the client side, the benefits of advanced packaging include smaller package size and lower power consumption (for Lakefield, Intel claims a 10x SoC standby power improvement at 2.6mW). In the data center, advanced packaging will help to build very large and powerful platforms on a single package, with performance, latency, and power characteristics close to what a monolithic die would yield. The yield advantage of small chiplets and the establishment of chipset ecosystem are major drivers, too.

Also at The Register, VentureBeat, Guru3D, and PCWorld.

Related: Intel Core i7-8809G with Radeon Graphics and High Bandwidth Memory: Details Leaked
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More
Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan


Original Submission

AMD and Intel at Computex 2019: First Ryzen 3000-Series CPUs and Navi GPU Announced 20 comments

At Computex 2019 in Taipei, AMD CEO Lisa Su gave a keynote presentation announcing the first "7nm" Navi GPU and Ryzen 3000-series CPUs. All of the products will support PCI Express 4.0.

Contrary to recent reports, AMD says that the Navi microarchitecture is not based on Graphics Core Next (GCN), but rather a new "RDNA" macroarchitecture ('R' for Radeon), although the extent of the difference is not clear. There is also no conflict with Nvidia's naming scheme; the 5000-series naming is a reference to the company's 50th anniversary.

AMD claims that Navi GPUs will have 25% better performance/clock and 50% better performance/Watt vs. Vega GPUs. AMD Radeon RX 5700 is the first "7nm" Navi GPU to be announced. It was compared with Nvidia's GeForce RTX 2070, with the RX 5700 outperforming the RTX 2070 by 10% in the AMD-favorable game Strange Brigade. Pricing and other launch details will be revealed on June 10.

AMD also announced the first five Ryzen 3000-series CPUs, all of which will be released on July 7:

CPUCores / ThreadsFrequencyTDPPrice
Ryzen 9 3900X12 / 243.8 - 4.6 GHz105 W$499
Ryzen 7 3800X8 / 163.9 - 4.5 GHz105 W$399
Ryzen 7 3700X8 / 163.6 - 4.4 GHz65 W$329
Ryzen 5 3600X6 / 123.8 - 4.4 GHz95 W$249
Ryzen 5 36006 / 123.6 - 4.2 GHz65 W$199

The Ryzen 9 3900X is the only CPU in the list using two core chiplets, each with 6 of 8 cores enabled. AMD has held back on releasing a 16-core monster for now. AMD compared the Ryzen 9 3900X to the $1,189 Intel Core i9-9920X, the Ryzen 7 3800X to the $499 Intel Core i9-9900K, and the Ryzen 7 3700X to the Intel Core i7-9700K, with the AMD chips outperforming the Intel chips in certain single and multi-threaded benchmarks (wait for the reviews before drawing any definitive conclusions). All five of the processors will come with a bundled cooler, as seen in this list.

Intel Launches a Wi-Fi 6 (802.11ax) Wireless Network Adapter 12 comments

Intel Launches Wi-Fi 6 AX200 Wireless Network Adapter

Intel has quietly launched its first Wi-Fi 6 (802.11ax) wireless network adapter, codenamed Cyclone Peak. The new WLAN adapter will deliver up to 2.4 Gbps network throughput when used with a compatible access point, but, like Wi-Fi 6 in general, its main advantage is that it will work better than existing adapters in RF-noisy environments where multiple Wi-Fi networks co-exist.

The Intel Wi-Fi 6 AX200 is a CNVi WLAN card that supports 802.11ax via 2x2 MU-MIMO antennas over the 2.4 GHz and 5 GHz bands. And never found too far from a Wi-Fi card, Intel's AX200 also supports Bluetooth 5.0.

[...] Intel's web-site says that the first Cyclone Peak wireless network adapter has been launched, so the device is available to makers of PCs. Depending on the order, the Intel Wi-Fi 6 AX200 costs Intel's customers from $10 to $17.

One of the commenters linked to this paper about 802.11be, a generation of Extremely High Throughput (EHT) Wi-Fi technology beyond 802.11ax that could offer a maximum throughput of at least 30 Gbps.

Previously: Netgear Introduces its First Wi-Fi 6 (802.11ax) Routers

Related: Wi-Fi Alliance Rebrands Wi-Fi Standards
Qualcomm Announces 802.11ay Wi-Fi Chips that Can Transmit 10 Gbps Within Line-of-Sight
Intel Promises "10nm" Chips by the End of 2019, and More


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