from the processing-in-a-disorderly-manner dept.
SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP
In the last few year's we've seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we've seen a lot of vendors make the switch from licensing Arm's architecture and IP designs to the open-source RISC-V architecture and either licensed or custom-made IP based on the ISA. While many vendors do choose to design their own microarchitectures to replace Arm-based microcontroller designs in their products, things get a little bit more complicated once you scale up in performance. It's here where SiFive comes into play as a RISC-V IP vendor offering more complex designs for companies to license – essentially a similar business model to Arm's – just that it's based on the new open ISA.
Today's announcement marks a milestone in SiFive's IP offering as the company is revealing its first ever out-of-order CPU microarchitecture, promising a significant performance jump over existing RISC-V cores, and offering competitive PPA metrics compared to Arm's products. [...] SiFive's design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. The A72 is quite an old comparison point by now, however SiFive's PPA targets are comparatively quite high, meaning the U8 should be quite competitive to Arm's latest generation cores.
Performance gains over previous designs are substantial:
The performance increases compared to previous generation SiFive cores are extremely impressive: Against a U54 at ISO-process, the new U84 features a 5.3x performance increase in SPECint2006. When taking into account the process node improvements that allow the U84 to clock higher, the generational increases that we'd be seeing in products will be more akin to a factor of 7.2x.
In terms of PPA, compared to a U7-series CPU, IPC increases come in at 2.3x resulting in 3.1x higher performance (ISO-process). A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.
On the same 7nm process, the U84 lands in at 0.28mm² per core and a cluster comprising four cores and a 2MB L2 cache measure in at 2.63mm². For comparison, an Arm Cortex-A55 as measured on the Kirin 980, also on 7nm, a core with its 128KB private L2 cache comes in at 0.36mm². Given that SiFive promises of similar performance to a Cortex-A72, which in turn would be more than double the performance of an A55, it looks like SiFive's U84 core would be extremely competitive in terms of its PPA.
Related: Qualcomm Invests in RISC-V Startup SiFive
Related Stories
SiFive to Debut RISC-V PC for Developers based on Freedom U740 next-gen SoC
In recent years, people have discussed the need to have Arm-based PCs or workstations for developers to work directly on the target hardware, and there are now several options including SynQuacer E-Series 24-Core Arm PC, Ampere eMAG 64bit Arm Workstation, and HoneyComb LX2K 16-core Arm Workstation.
Now it appears we'll soon get something similar for RISC-V architecture with SiFive to debut the first RISC-V PC for developers at the Linley Fall Processor Conference 2020 taking place on October 20-22 and October 27-29. The PC will be powered by Freedom U740 next-generation RISC-V processor that will also be introduced at the event.
We have very few details about this point in time, but the company points the SiFive Freedom U740 (FU740) SoC will enable professional developers to create RISC-V applications from bare-metal to Linux-based. The processor is said to combines[sic] a heterogeneous mix+match core complex with modern PC expansion capabilities, which probably means PCIe, SATA etc.., and the company will provide tools to ease professional software development.
Freedom U740 details are unknown, but Freedom U540 is a quad-core CPU that was used in the HiFive Unleashed single-board computer.
Related: SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)
[According] to Bloomberg, Intel has reportedly offered over $2 billion to acquire the fabless semiconductor SiFive, a provider of commercial RISC-V processor IP and silicon solutions based on the RISC-V instruction set architecture.
Should this deal become a reality, it would mark the climax of growing bonhomie between Intel and SiFive. For instance, back in 2018, Intel was one of the participants in the Series C funding round of SiFive. Thereafter, in March 2021, SiFive announced a collaboration with the Intel Foundry Business (IFB) to develop innovative new RISC-V computing platforms.
Of course, unlike legacy Instruction Set Architectures (ISAs), RISC-V's proponents believe that it addresses the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, given that that the ISA is layered, extensible, and flexible. It is hardly surprising, therefore, that some believe RISC-V to be the future.
Bear in mind that SiFive was last valued at $500 million, as per the data available at PitchBook. This means that Intel would be paying a premium of over 300 percent relative to SiFive's 2020 valuation.
Previously: SiFive HiFive Unleashed Not as Open as Previously Thought
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)
SiFive to Debut a RISC-V PC for Developers in October
SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs
GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+
GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.
The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company's RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries' 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices [using] GloFo's advanced fab technology.
GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.
Related: Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages
SK Hynix Announces HBM2E Memory for 2020 Release
GlobalFoundries Develops "12LP+" Fabrication Process
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
Qualcomm Invests in RISC-V Startup SiFive
Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups.
Last fall, Esperanto Technologies announced a $58 million funding round. The chip IP vendor is incorporating more than 1,000 RISC-V cores onto a single 7-nm chip. Data storage specialist Western Digital is an early investor in Esperanto, Mountain View, Calif.
This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.
Observers note that wireless modem leader Qualcomm is among Arm's biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of Shanghai along with Sutter Hill Ventures and Spark Capital. Intel Capital and Western Digital also were early investors.
Also at EE Times.
See also: SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
Previously: RISC-V Projects to Collaborate
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare
SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance
Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
Esperanto Technologies and SiFive look like the names to watch.
Related: First Open Source RISC-V Implementations Become Available
Western Digital Unveils RISC-V Controller Design
Raspberry Pi Foundation Announces RISC-V Foundation Membership
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License
(Score: 2) by shortscreen on Thursday October 31 2019, @04:23AM (5 children)
How many instructions executed at once? Or are these still single pipe? In the x86 timeline, superscalar came first.
(Score: 3, Insightful) by Anonymous Coward on Thursday October 31 2019, @06:02AM (4 children)
I'm curious about that too. But honestly, I'd rather not even go down the rabbit hole of branch prediction and OOO execution. Haven't we had enough MELTDOWNs and SPECTREs yet?
What good is a more MIPS when all you're doing is running insecure code faster and faster?
(Score: 2) by Unixnut on Thursday October 31 2019, @03:45PM
Indeed, also I think superscalar architecture is not as desirable now as it was back when it came out for x86.
Superscalar came out to mass adoption with the original "Pentium" processor in the 90s. That was a ~60MHz single core CPU, and it was expensive. So if you could make more efficient use of your single expensive silicon, great! Superscalar made sense back then, because it reduced the time your expensive silicon stayed idle.
However we are now going full bore to massively multicore machines, with ability to control per core idle power. Moore's law has resulted in CPUs being so cheap to implement that rather than going with superscalar architecture (or other fancy trickery), it might well be easier/cheaper to just add another core to your design instead (not to mention simpler, and less likely to be insecure).
(Score: 2) by DannyB on Thursday October 31 2019, @03:47PM (2 children)
I vaguely remember back in the 90's learning a little about Power PC (on classic Mac). The conditional branch instruction could specify whether the developer (or compiler) expected the branch to be more likely to be taken or not. I could go for that. If that bit in the instruction is wrong once the branch condition is fully known, then some efficiency is lost. But only one path is speculatively executed, not two.
The server will be down for replacement of vacuum tubes, belts, worn parts and lubrication of gears and bearings.
(Score: 1, Interesting) by Anonymous Coward on Thursday October 31 2019, @07:14PM (1 child)
You can do that now. Both the developer and the compiler can determine how the conditional jumps are likely to execute (through things like explicit marking or PGO). The compiler then selects the proper jump instruction based on the expected outcome. The problem is that even if you have this sort of speculative execution, you theoretically still at risk for some of the attacks.
(Score: 2) by DannyB on Thursday October 31 2019, @08:19PM
+1 Thanks
The server will be down for replacement of vacuum tubes, belts, worn parts and lubrication of gears and bearings.
(Score: 2) by RamiK on Thursday October 31 2019, @05:06PM (6 children)
They get what takes the other fabless 5years done under 3 or even 2 years and with a small team. And they deliver with an open source compiler... Mighty impressive.
compiling...
(Score: 1, Insightful) by Anonymous Coward on Thursday October 31 2019, @06:45PM (4 children)
we need open designs, not licensed designs. change your usurious business model.
(Score: 2) by DannyB on Thursday October 31 2019, @08:26PM
I agree.
It's the same old argument and history playing out but in hardware.
fanboy: "But Windows isn't that expensive, in fact it's include on the PC and subsidized by the included malware. It's great!"
But I believed even in 2000 that open source would win. Trying to stop it is like trying to stop the incoming tide on the beach by using your hands. Or trying to prevent the sun from shining by holding your hands up in the sky to cover the sun. The force of open grows and in time becomes overwhelming. But proprietary sure did beat it for marketing, short term penetration, and a seeming gloss of skin deep quality. But here we are today and Linux and other open source powers everything. Microsoft is trying to embrace it all as fast as they can.
It will be the same with hardware. Some closed designs. But I think open is what will ultimately win. I would simply ask what was it that motivated the entire RISC-V design and effort in the first place? Those motives are still in play. And more and more users will realize how those open motives benefit them in a tangible way, while the addictive sweetness of proprietary is like a drug dealer's first hit for free.
The server will be down for replacement of vacuum tubes, belts, worn parts and lubrication of gears and bearings.
(Score: 2) by RamiK on Thursday October 31 2019, @09:33PM (2 children)
Not me. The purpose of free open software is to prevent vendor locks from the hardware side to the developer's side and from the developer's side to the end-customer. The purpose of a free and open ISA is to prevent vendor lock from the hardware side to the developer's side. What's the purpose of a free and open design? The fabs can't become a natural monopoly due to geopolitical competition preventing any one country from charging too much. The fabless can't become a natural monopoly thanks to the market demanding the use of free and open ISAs especially from the compiler and kernel people.
Even from a security standpoint they're useless since we have no way to validate what they're actually manufacturing.
So no. We don't need open designs. It would be nice for society's progress if the different parties could collaborate instead of compete. But it's also a good space for some competition.
That being said, for smaller cores the design should be open. There's nothing to improve in those spaces so it's just wasting everyone's resources to have competing designs at the micro-controller space.
compiling...
(Score: 0) by Anonymous Coward on Saturday November 02 2019, @06:26PM (1 child)
"What's the purpose of a free and open design?"
there's a lot i don't know about hardware design and manufacturing, but in the future i want people to be able to print a board from a spec file at home or buy parts like this via a distributed ledger type app that orders one from some person who designed their own and prints in their garage or small town coop or something. i'm sick of big companies controlling everything. i'm not concerned about whether one country's huge company can grow beyond it's borders. i want power for the individual.
(Score: 2) by RamiK on Saturday November 02 2019, @08:30PM
You might get decent enough PCB desktop printers soon that print out commercial grade boards. Maybe they'll even do SMT placing to some extent for some very odd repair service jobs. But short of magic grade technological leaps, the individual components are always going to be sourced from factories and will always cost dozens of times more to purchase individually than in bulk.
Look, I love Emerson and transcendentalism as much as the next guy, but this whole self-reliance dream been done to death as far back as Brook Farm [wikipedia.org].
Only empowerment individual get in modern society is through making sure there's competition on the supply's side. Open design when you need a whole industrial chain to produce those designs is about as open as give the Windows source code to the Amish.
compiling...
(Score: 2) by driverless on Sunday November 03 2019, @02:33AM
They're crazy good at manipulating figures. Look up what PPA means. It wouldn't surprise me if a 6502 (built with current tech, not 1970s hand-laid-out rubylith) had better PPA figures than a SiFive CPU.