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posted by martyb on Thursday February 01 2018, @07:16AM   Printer-friendly
from the you-are-in-a-maze-of-tiny-little-transistors-all-alike dept.

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

Related Stories

Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap 2 comments

Samsung has shipped 70,000 silicon wafers worth of "10nm Low Power Early" chips, and is planning a supposed 6 nanometer process. The company implies that it will make 8nm and 6nm chips in addition to 10nm and 7nm:

It's looking like Samsung will be the first company to manufacture 10nm chips, besting both Intel and TSMC. Samsung has also already set its eyes on the 8nm, 7nm, and 6nm process technologies. The 8nm and 6nm processes will likely be follow-up technologies to the 10nm and 7nm processes, respectively.

The company is expected to reach 7nm by 2019, a move that could be enabled by its partnership with IBM. The company may also use EUV lithography for its 7nm process, but it's not yet clear whether EUV lithography will be available for the first ever 7nm process iteration. Intel has hinted before that it may not adopt EUV lithography until the 5nm process generation. Samsung will reveal more details about its roadmap, including the 8nm and 6nm process generations, at the upcoming U.S Samsung Foundry Forum scheduled for May 24, 2017.

Samsung press release.


Original Submission

Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's 15 comments

Intel is talking about improvements it has made to transistor scaling for the 10nm process node, and claims that its version of 10nm will increase transistor density by 2.7x rather than doubling it.

On the face of it, three years between process shrinks, rather than the traditional two years, would appear to end Moore's Law. But Intel claims that's not so. The company says that the 14nm and 10nm process shrinks in particular more than doubled the transistor density. At 10nm, for example, the company names a couple of techniques that are enabling this "hyperscaling." Each logic cell (an arrangement of transistors to form a specific logic gate, such as a NAND gate or a flip flop) is surrounded by dummy gates: spacers to isolate one cell from its neighbor. Traditionally, two dummy gates have been used at the boundary of each cell; at 10nm, Intel is reducing this to a single dummy gate, thereby reducing the space occupied by each cell and allowing them to be packed more tightly.

Each gate has a number of contacts used to join them to the metal layers of the chip. Traditionally, the contact was offset from the gate. At 10nm, Intel is stacking the contacts on top of the gates, which it calls "contact over active gate." Again, this reduces the space each gate takes, increasing the transistor density.

Samsung Plans a "4nm" Process 12 comments

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.

Source.

But how many transistors per square millimeter is it?


Original Submission

GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm 9 comments

GlobalFoundries: Next-generation chip factories will cost at least $10 billion

The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost between $10 billion and $12 billion to build a next-generation chip factory based on the latest technology, dubbed 7-nanometer production. And one for the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.

There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factory.

Dean Takahashi from VentureBeat interviewed Sanjay Jha, CEO of GlobalFoundries:

Basically, the numbers don't mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don't know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It's not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.

TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020 9 comments

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


Original Submission

TSMC Will Build a $12 Billion "5nm" Fab in Arizona 16 comments

TSMC to build a $12 billion advanced semiconductor plant in Arizona with U.S. government support

Taiwan Semiconductor Manufacturing Co., the world's largest contract semiconductor foundry, said today that it plans to build an advanced chip foundry in Arizona with support from the state and the United States federal government.

The announcement follows a Wall Street Journal report earlier this week that White House officials were in talks with TSMC and Intel to build foundries in the U.S., as part of its effort to reduce reliance on chip factories in Asia. Based in Hsinchu, Taiwan, TSMC provides chip components for many of the world's largest semiconductor companies and its U.S. clients include Apple and Qualcomm.

The plant, scheduled to start production of chips in 2024, will enable TSMC's American customers to fabricate their semiconductor products domestically. It will use the company's 5-nanometer technology and is expected to create 1,600 jobs and have the capacity to produce 20,000 wafers a month.

The U.S.-China trade war, national security concerns, geopolitical unrest and the COVID-19 pandemic have all underscored the shortfalls of relying on foundries located abroad and international supply chains.

The U.S. government has reportedly been in talks with TSMC for months, though one sticking point for the company was the high cost of building a new foundry. TSMC chairman Mark Liu told the New York Times in October that the project would require major subsidies because it is more expensive to operate a factory in the U.S. than in Taiwan.

Also at AnandTech, The Verge, CNN, South China Morning Post, Wccftech, and Bloomberg.

Previously: U.S. Attempting to Restrict TSMC Sales to Huawei
Washington in Talks with Chipmakers about Building U.S. Factories

Related: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Has Started Development of a "2nm" Process Node


Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.

[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).

So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process 2 comments

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

"3nm" Test Chip Taped Out by Imec and Cadence 13 comments

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Samsung Preparing to Build Another Memory Fab Near Pyeongtaek for $27.8 Billion 5 comments

Samsung Preps to Build Another Multi-Billion Dollar Memory Fab Near Pyeongtaek

Samsung has begun preparations to build another semiconductor production facility near Pyeongtaek, South Korea. The fab will produce various types of memory as the market demands, and if unofficial information is correct, the new fab may be larger than the adjacent fab that began operations last year.

At present the upcoming fab is called the P2 Project and it will be located adjacent to the existing fab near Pyeongtaek. Samsung has already started to establish infrastructure for the production facility — it ordered the construction of gas pipes for the new production facility in January and is expected to start other works shortly. ETNews reports that Samsung is looking at investing ₩30 trillion ($27.8 billion) in the new P2 Project facility, but does not elaborate whether the number represents total investments, or initial investments. ₩30 trillion is the total amount of money that Samsung has already invested and plans to invest in its existing fab near Pyeongtaek by 2021. Considering the fact that the P2 is in an early stage of planning, it is unlikely that the company has finalized its investments plans.

Related: Samsung Set to Outpace Intel in Semiconductor Revenues
Samsung Could Boost NAND Production Capacity, WD Intervenes in Toshiba Memory Sale
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
Samsung's Second Generation 10nm-Class DRAM in Production
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Another Step Toward the End of Moore's Law 16 comments

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

TSMC Will Make AMD's "7nm" Epyc Server CPUs 4 comments

AMD "Rome" EPYC CPUs to Be Fabbed By TSMC

AMD CEO Lisa Su has announced that second-generation "Rome" EPYC CPU that the company is wrapping up work on is being produced out at TSMC. This is a notable departure from how things have gone for AMD with the Zen 1 generation, as GlobalFoundries has produced all of AMD's Zen CPUs, both for consumer Ryzen and professional EPYC parts.

[...] As it stands, AMD seems rather optimistic about how things are currently going. Rome silicon is already back in the labs, and indeed AMD is already sampling the parts to certain partners for early validation. Which means AMD remains on track to launch their second-generation EPYC processors in 2019.

[...] Ultimately however if they are meeting their order quota from GlobalFoundries, then AMD's situation is ultimately much more market driven: which fab can offer the necessary capacity and performance, and at the best prices. Which will be an important consideration as GlobalFoundries has indicated that it may not be able to keep up with 7nm demand, especially with the long manufacturing process their first-generation DUV-based 7nm "7LP" process requires.

See also: No 16-core AMD Ryzen AM4 Until After 7nm EPYC Launch (2019)

Related: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
AMD Returns to the Datacenter, Set to Launch "7nm" Radeon Instinct GPUs for Machine Learning in 2018
AMD Ratcheting Up the Pressure on Intel
More on AMD's Licensing of Epyc Server Chips to Chinese Companies


Original Submission

TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April 13 comments

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack


Original Submission

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  • (Score: 2) by TheRaven on Thursday February 01 2018, @10:11AM (1 child)

    by TheRaven (270) on Thursday February 01 2018, @10:11AM (#631400) Journal
    Anyone remember back in the days when the size for a process meant the size of the smallest feature, or even further back when it meant the size of something actually useful, rather than just a 'hey, look, I have a smaller number than you!' marketing thing?
    --
    sudo mod me up
    • (Score: 0) by Anonymous Coward on Thursday February 01 2018, @11:47AM

      by Anonymous Coward on Thursday February 01 2018, @11:47AM (#631430)

      I thought it meant the size of the conductive tracks between components on the chip.

  • (Score: 0) by Anonymous Coward on Friday February 02 2018, @01:55AM

    by Anonymous Coward on Friday February 02 2018, @01:55AM (#631831)

    Once AMD or Intel release their 12nm or 10nm CPU I will upgrade...

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